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Multiple Fault Detection in Fan-Out Free Circuits Using Minimal Single Fault Test Set
June 1996 (vol. 45 no. 6)
pp. 763-765
ASCII Text
x 
 
K. Lai, P.k. Lala, "Multiple Fault Detection in Fan-Out Free Circuits Using Minimal Single Fault Test Set," IEEE Transactions on Computers, vol. 45, no. 6, pp. 763-765, June, 1996.
 
 
BibTex
x
 
@article{ 10.1109/12.506433,
author = {K. Lai and P.k. Lala},
title = {Multiple Fault Detection in Fan-Out Free Circuits Using Minimal Single Fault Test Set},
journal ={IEEE Transactions on Computers},
volume = {45},
number = {6},
issn = {0018-9340},
year = {1996},
pages = {763-765},
doi = {http://doi.ieeecomputersociety.org/10.1109/12.506433},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - Multiple Fault Detection in Fan-Out Free Circuits Using Minimal Single Fault Test Set
IS - 6
SN - 0018-9340
SP763
EP765
EPD - 763-765
A1 - K. Lai,
A1 - P.k. Lala,
PY - 1996
KW - Multiple faults
KW - fan-out-free circuit
KW - output count
KW - test generation.
VL - 45
JA - IEEE Transactions on Computers
ER -
 

Abstract—This paper presents a new algorithm to generate test sets for single stuck-at faults, which also detect all multiple stuck-at faults in fan-out-free circuits. This algorithm derives the test set for each node in a fan-out-free circuit by calculating the output count of the node. The output count indicates the number of test patterns needed to check for all faults in the corresponding subcircuit. The fan-out-free circuit can be any combination of AND, OR, NOT, NAND, and NOR gates.

[1] I. Kohavi and Z. Kohavi, "Detection of Multiple Faults in Combinational Logic Network," IEEE Trans. Computers, vol. 21, no. 6, pp. 556-568, June 1972.
[2] J.W. Gault, J.P. Robinson, and S.M. Reddy, "Multiple Fault Detection in Combinational Networks," IEEE Trans. Computers, vol. 21, no. 1, pp. 31-36, Jan. 1972.
[3] M.W. Du and C.D. Weiss, "Multiple Fault Detection in Combinational Circuits," IEEE Trans. Computers, vol. 22, no. 3, pp. 235-240, Mar. 1973.
[4] G. Fantauzzi and A. Marsella, "Multiple -Fault Detection Location in Fan-Out Free Combinational Circuits," IEEE Trans. Computers, vol. 23, no. 1, pp. 48-55, Jan. 1974.
[5] S.S. Yau and S.C. Yang, "Multiple Fault Detection for Combinational Logic Circuits," IEEE Trans. Computers, vol. 24, no. 3, pp. 233-242, Mar. 1975.
[6] W. Jone and P.H. Madden, "Multiple Fault Testing Using Minimal Single Fault Test Set for Fan-Out-Free Circuits," IEEE Trans. Computer-Aided Design, vol. 12, no. 1, Jan. 1993.
[7] D.C. Bossen and .J. Hong, "Cause-Effect Analysis for Multiple Fault Detection in Combinational Network," IEEE Trans. Computer-Aided Design, pp. 1,252-1,257, Nov. 1971.
[8] D.R. Schertz and G. Metze, "On the Design of Multiple Fault Diagnosable Networks," IEEE Trans. Computers, vol. 20, no. 11, pp. 1,361-1,364, Nov. 1971.
[9] D.R. Schertz and G. Metze, "A New Representation for Faults in Combinational Digital Circuits," IEEE Trans. Computers, vol. 21, no. 6, pp. 858-866, Aug. 1972.
[10] J.P. Hayes, "A NAND Model for Fault Diagnosis in Combinational Logic Network," IEEE Trans. Computers, vol. 20, no. 12, pp. 1,496-1,506, Dec. 1971.
[11] H. Cox and J. Rajski, "A Method of Fault Analysis for Test Generation and Fault Diagnosis," IEEE Trans. Computer-Aided Design, July 1988.

Index Terms:
Multiple faults, fan-out-free circuit, output count, test generation.
Citation:
K. Lai, P.k. Lala, "Multiple Fault Detection in Fan-Out Free Circuits Using Minimal Single Fault Test Set," IEEE Transactions on Computers, vol. 45, no. 6, pp. 763-765, June 1996, doi:10.1109/12.506433
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