|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
| | ||
| Search | ||
| ||
| ASCII Text | x | ||
| Sandeep N. Bhatt, Gianfranco Bilardi, Geppino Pucci, Abhiram Ranade, Arnold L. Rosenberg, Eric J. Schwabe, "On Bufferless Routing of Variable Length Messages in Leveled Networks," IEEE Transactions on Computers, vol. 45, no. 6, pp. 714-729, June, 1996. | |||
| BibTex | x | ||
| @article{ 10.1109/12.506427, author = {Sandeep N. Bhatt and Gianfranco Bilardi and Geppino Pucci and Abhiram Ranade and Arnold L. Rosenberg and Eric J. Schwabe}, title = {On Bufferless Routing of Variable Length Messages in Leveled Networks}, journal ={IEEE Transactions on Computers}, volume = {45}, number = {6}, issn = {0018-9340}, year = {1996}, pages = {714-729}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.506427}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - On Bufferless Routing of Variable Length Messages in Leveled Networks IS - 6 SN - 0018-9340 SP714 EP729 EPD - 714-729 A1 - Sandeep N. Bhatt, A1 - Gianfranco Bilardi, A1 - Geppino Pucci, A1 - Abhiram Ranade, A1 - Arnold L. Rosenberg, A1 - Eric J. Schwabe, PY - 1996 KW - Processor networks KW - interprocessor communication KW - message scheduling KW - routing algorithms KW - all-to-all communication KW - high-level communication primitives. VL - 45 JA - IEEE Transactions on Computers ER - | |||
Abstract—We study the most general communication paradigm on a multiprocessor, wherein each processor has a distinct message (of possibly distinct lengths) for each other processor. We study this paradigm, which we call
[1] B. Aiello, F.T. Leighton, B. Maggs, and M. Newman, "Fast Algorithms for Bit-Serial Routing on a Hypercube," Math. Syst. Th., vol. 24, pp. 253-271, 1990.
[2] S.N. Bhatt, G. Pucci, A. Ranade, and A.L. Rosenberg, "Scattering and Gathering Messages in Networks of Processors," IEEE Trans. Computers, vol. 42, pp. 938-949, 1992.
[3] S. Borkar, R. Cohn, G. Cox, T. Gross, H.T. Kung, M. Lam, M. Levine, B. Moore, W. Moore, C. Peterson, J. Susman, J. Sutton, J. Urbanski, and J. Webb, "Supporting Systolic and Memory Communication in iWarp," Proc. 17th Int'l Symp. Computer Architecture, pp. 70-81, 1990.
[4] A. Borodin and J.E. Hopcroft,"Routing, merging and sorting on parallel models of comparison," J. Computer and System Science, vol. 30, pp. 130-145, 1985.
[5] W.J. Dally and C.L. Seitz, “Deadlock-Free Message Routing in Multiprocessor Interconnection Networks,” IEEE Trans. Computers, Vol. C-36, No. 5, May 1987, pp. 547-553.
[6] U. Feige and P. Raghavan, "Exact Analysis of Hot Potato Routing. 33rd Ann. Symp. Foundations of Computer Science, pp. 553-562, Oct. 1992.
[7] S. Felperin, P. Raghavan, and E. Upfal, "A Theory of Wormhole Routing in Parallel Computers," Proc. 33rd Ann. IEEE Conf. Foundations of Computer Science, pp. 563-572, 1992.
[8] R. Greenberg and H.-C. Oh, "Packet Routing in Networks with Long Wires," Proc. 30th Allerton Conf. Comm., Control, and Computing, pp. 664-673, 1992.
[9] H.A. Kierstead, "The Linearity of First-Fit Coloring of Interval Graphs," SIAM J. Discr. Math., vol. 1, pp. 526-530, 1988.
[10] H.A. Kierstead, "A Polynomial Time Approximation Algorithm for Dynamic Storage Allocation," Discr. Math., vol. 88, pp. 231-237, 1991.
[11] G. Kortsarz and D. Peleg, "Approximation Algorithms for Minimum Time Broadcast," Proc. 1992 Israel Symp. Theory of Computer Science, 1992.
[12] D.H. Lawrie and D.A. Padua, "Analysis of Message Switching with Shuffle-Exchanges in Multiprocessors," Interconnection Networks.New York: IEEE CS Press, 1984.
[13] T. Leighton, B. Maggs, A. Ranade, and S. Rao, "Randomized Routing and Sorting in Fixed-Connection Networks," J. Algorithms, vol. 17, no. 1, pp. 157-205, 1994.
[14] D.H. Linder and J.C. Harden, "An Adaptive and Fault Tolerant Wormhole Routing Strategy for k-Ary n-Cubes," IEEE Trans. Computers, vol. 40, no. 1, pp. 2-12, Jan. 1991.
[15] D. Peleg and J.D. Ullman, "An Optimal Synchronizer for the Hypercube," SIAM J. Computing, vol 18, pp. 740-747, 1989.
[16] D.B. Shmoys, C. Stein, and J. Wein, "Improved Approximation Algorithms for Shop Scheduling," SIAM J. Computing, vol. 23, pp. 617-632, 1994.
[17] L.G. Valiant, "Universality Considerations in VLSI Circuits," IEEE Trans. Computers, vol. 30, pp. 135-140, 1981.
[18] L.G. Valiant, "A Scheme for Fast Parallel Communication," SIAM J. Computing, vol. 11, pp. 350-361, 1982.
[19] L.G. Valiant, "Bulk-Synchronous Parallel Computers," Parallel Processing and Artificial Intelligence, M. Reeve and S.E. Zenith, eds., pp. 15-22.New York: Wiley, 1989.

