This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
A New Class Of Efficient Algorithms For Reconfiguration Of Memory Arrays
May 1996 (vol. 45 no. 5)
pp. 614-618

Abstract—In this paper, we present a new class of linear time heuristic algorithms for reconfiguring RRAMs. One novel feature of our algorithms is that we are able to derive new bounds on the fault counts for fast detection of reparable and irreparable RRAMs. Another novel feature is that, based on our algorithms, we are able to identify a new polynomial time solvable instance of the reconfiguration problem. Empirical results indicate that our new class of algorithms is indeed fast and effective.

[1] W. Che and I. Koren,"Fault Spectrum Analysis for Fast Spare Allocation in Reconfigurable Arrays," Proc. IEEE Int'l Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 60-69, Nov. 1992.
[2] R.C. Evans,"Testing Repairable RAMs and Mostly Good Memories," Proc. IEEE Int'l Test Conf., pp. 49-55, 1981.
[3] W.K. Fuchs and M. Chang,"Diagnosis and Repair of Large Memories: A Critical Review and Recent Results," Proc. IEEE Int'l Workshop on Defect and Fault Tolerance in VLSI Systems,New York: Plenum Press, pp. 213-225, 1988.
[4] R.L. Hadas and C.L. Liu,"FastSearch Algorithms for Reconfiguration Problems," Proc. IEEE Int'l Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 260-273, Nov. 1991.
[5] R. W. Haddad,A. T. Dahbura, and A. B. Sharma,"Increased Throughput for the Testing and Repair of RAMs with Redundancy," IEEE Trans. Computers, vol. 40, no. 2, pp. 154-166, Feb. 1991.
[6] V.G. Hemmady and S.M. Reddy,"On The Repair of Redundant RAMs," Proc. 26th ACM/IEEE Design Automation Conf., pp. 710-713, 1989.
[7] S.Y. Kuo and W.K. Fuchs,"Efficient Spare Allocation for Reconfigurable Arrays," IEEE Design and Test, vol. 4, no. 1, pp. 24-37, Feb. 1987.
[8] F. Lombardi and W.K. Huang,"Approaches for the repair of VLSI/WSI DRAMs by row/column deletion," Proc. 1988 Int'l Symp. Fault-Tolerant Computing, pp. 342-347, June 1988.
[9] S.E. Schuster,"Multiple Word/Bit Line Redundancy for Semiconductor Memories," IEEE J. Solid-State Circuits, vol. 13, no. 5, pp. 698-703, Oct. 1978.
[10] W.P. Shi and W.K. Fuchs,"Probabilistic Analysis and Algorithms for Reconfiguration of Memory Arrays," IEEE Trans. Computer-Aided Design, vol. 11, no. 9, pp. 1,153-1,160, Sept. 1992.
[11] J.J. Shen and I. Koren,"On Defect Generation Processes for Yield Estimation Through Simulation," Proc. IEEE Int'l Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 238-247, Oct. 1989.
[12] C.H. Stapper,"Large-area Fault Clusters and Fault Tolerance in VLSI Circuits: A Review," IBM J. Research and Development, vol 33, no. 2, pp. 162-173, Mar. 1989.
[13] M. Tarr,D. Boudreau, and R. Murphy,"Defect Analysis System Speeds Test and Repair of Redundant Memories," Electronics, pp. 175-179, Jan. 1984.
[14] C.L. Wey and F. Lombardi,"On the Repair of Redundant RAMs," IEEE Trans. Computer-Aided Design, vol. 6, no. 2, pp. 222-231, Mar. 1987.

Index Terms:
RRAMs, sparsity, throughput, vertex covers, NP-completeness, heuristic algorithms.
Citation:
C.p. Low, H.w. Leong, "A New Class Of Efficient Algorithms For Reconfiguration Of Memory Arrays," IEEE Transactions on Computers, vol. 45, no. 5, pp. 614-618, May 1996, doi:10.1109/12.509914
Usage of this product signifies your acceptance of the Terms of Use.