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Hierarchical Execution to Speed Up Pipeline Interlock in Mainframe Computers
May 1996 (vol. 45 no. 5)
pp. 589-599

Abstract—This paper introduces a methodology, called hierarchical execution, which reduces stalls caused by pipeline interlocks such as data and control dependencies. Since a lot of software has been accumulated in mainframe computer systems as object code, it is important to improve performance without having to recompile the code for optimization. Our methodology consists of a simple pre-ALU that generates results, with shorter latency than the main ALU, asynchronously, which reduces the overhead especially for address generation interlocks and branch instructions. This method was implemented in Hitachi's mainframe processors, M-680 and M-880. In M-680, the pre-ALU, together with the instruction decoder, processes instructions in superpipelined fashion, which further improves performance. The aggregate effect of hierarchical execution on CPU time, for evaluated benchmarks, is 10% on average, with only a 1.6% increase in hardware. Therefore, we can roughly say that the hierarchical execution method improved cost performance by 8%.

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Index Terms:
Benchmark, code optimization, compiler, hierarchical execution, mainframe computer, pipeline.
Yooichi Shintani, Toru Shonai, Hiroshi Kurokawa, Kazunori Kuriyama, Akira Yamaoka, "Hierarchical Execution to Speed Up Pipeline Interlock in Mainframe Computers," IEEE Transactions on Computers, vol. 45, no. 5, pp. 589-599, May 1996, doi:10.1109/12.509910
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