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| Manoj Franklin, Gurindar S. Sohi, "ARB: A Hardware Mechanism for Dynamic Reordering of Memory References," IEEE Transactions on Computers, vol. 45, no. 5, pp. 552-571, May, 1996. | |||
| BibTex | x | ||
| @article{ 10.1109/12.509907, author = {Manoj Franklin and Gurindar S. Sohi}, title = {ARB: A Hardware Mechanism for Dynamic Reordering of Memory References}, journal ={IEEE Transactions on Computers}, volume = {45}, number = {5}, issn = {0018-9340}, year = {1996}, pages = {552-571}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.509907}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - ARB: A Hardware Mechanism for Dynamic Reordering of Memory References IS - 5 SN - 0018-9340 SP552 EP571 EPD - 552-571 A1 - Manoj Franklin, A1 - Gurindar S. Sohi, PY - 1996 KW - Address Resolution Buffer (ARB) KW - dynamic scheduling KW - memory address disambiguation KW - speculative execution KW - unresolved memory references. VL - 45 JA - IEEE Transactions on Computers ER - | |||
Abstract—To exploit instruction level parallelism, it is important not only to execute multiple memory references per cycle, but also to reorder memory references(especially to execute loads before stores that precede them in the sequential instruction stream. To guarantee correctness of execution in such situations, memory reference addresses have to be disambiguated. This paper presents a novel hardware mechanism, called an
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