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  • 1996
  • Issue No. 4 - April
  • Abstract - A Generalization of the Single b-Bit Byte Error Correcting and Double Bit Error Detecting Codes for High-Speed Memory Systems
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A Generalization of the Single b-Bit Byte Error Correcting and Double Bit Error Detecting Codes for High-Speed Memory Systems
April 1996 (vol. 45 no. 4)
pp. 508-511

Abstract—In this paper, a general method using the subsets (generating sets) of GF(2b) for constructing the SbEC-DED codes will be presented. The constructions given in [1] are special cases of ours. For some values of b, the generating sets used in our constructions are larger than the cosets used in [1]. Hence, a larger code length can be obtained.

[1] E. Fujiwara and M. Hamada,"Single b-Bit Byte Error Correcting and Double Bit Error Detecting Codes for High-Speed Memory Systems," FTCS 22nd Ann. Int'l Symp. Fault-Tolerant Computing, vol. 8-9, no. 7, pp. 1,359-1,363, 1992.
[2] C.L. Chen,"Error Correcting Codes with Byte Error-Detection Capability," IEEE Trans. Computers, vol. 32, no. 7, pp. 615-621, July 1983.
[3] R.H. Deng and D.J. Costello Jr.,"Decoding of DBEC-TBED Reed-Solomon Codes," IEEE Trans. Computers, vol. 36, no. 11, pp. 1,359-1,363, Nov. 1987.
[4] S.J. Hong and A.M. Patel,"A General Class of Maximal Codes for Computer Applications," IEEE Trans. Computers, vol. 21, no. 12, pp. 1,322-1,331, Dec. 1972.
[5] T.R.N. Rao and Fujiwara, Error-Coding for Computer Systems.Englewood Cliffs, N.J.: Prentice Hall, 1989.
[6] A.M. Patel,"Error Recovery Scheme for the IBM 3850 Mass Storage System," IBM J. Research and Development, vol. 24, no. 1, pp. 32-42, 1980.

Index Terms:
High-speed memories, byte error-correcting/detecting codes, companion matrix, primitive polynomials, subfields/cosets.
Citation:
Sihai Xiao, Xiaofa Shi, Guiliang Feng, T.r.n. Rao, "A Generalization of the Single b-Bit Byte Error Correcting and Double Bit Error Detecting Codes for High-Speed Memory Systems," IEEE Transactions on Computers, vol. 45, no. 4, pp. 508-511, April 1996, doi:10.1109/12.494112
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