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Min-Cut Partitioning on Underlying Tree and Graph Structures
April 1996 (vol. 45 no. 4)
pp. 470-474

Abstract—We consider two generalizations of the min-cut partitioning problem where the nodes of a circuit C are to be mapped to the vertices of an underlying graph G, and the cost function to be minimized is the cost of associating the nets of C with the edges of G. Let P be the number of pins, t be the number of nodes of G, and d be the maximum number of cells on a net of C. In the first problem the graph G is a tree T. An iterative improvement heuristic is given in [9] with O(P·t3) time per pass. Our proposed heuristic guarantees identical solutions in O(P·t· min{d, t}) time per pass. The second problem is defined on any graph G. The standard iterative improvement heuristic requires O(P·t4) time per pass, but our proposed approach guarantees O(P·t· min{d, t}) time per pass. The problems find applications in VLSI physical design and in distributed systems.

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Index Terms:
Circuit and network partitioning, iterative improvement, NP-hard.
Citation:
Spyros Tragoudas, "Min-Cut Partitioning on Underlying Tree and Graph Structures," IEEE Transactions on Computers, vol. 45, no. 4, pp. 470-474, April 1996, doi:10.1109/12.494104
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