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Issue No.04 - April (1996 vol.45)
pp: 470-474
ABSTRACT
<p><b>Abstract</b>—We consider two generalizations of the min-cut partitioning problem where the nodes of a circuit <it>C</it> are to be mapped to the vertices of an underlying graph <it>G</it>, and the cost function to be minimized is the cost of associating the nets of <it>C</it> with the edges of <it>G</it>. Let <it>P</it> be the number of pins, <it>t</it> be the number of nodes of <it>G</it>, and <it>d</it> be the maximum number of cells on a net of <it>C</it>. In the first problem the graph <it>G</it> is a tree <it>T</it>. An iterative improvement heuristic is given in [<ref rid="bibt04709" type="bib">9</ref>] with <it>O</it>(<it>P</it>·<it>t</it><super>3</super>) time per pass. Our proposed heuristic guarantees identical solutions in <it>O</it>(<it>P</it>·<it>t</it>· min{<it>d</it>, <it>t</it>}) time per pass. The second problem is defined on any graph <it>G</it>. The standard iterative improvement heuristic requires <it>O</it>(<it>P</it>·<it>t</it><super>4</super>) time per pass, but our proposed approach guarantees <it>O</it>(<it>P</it>·<it>t</it>· min{<it>d</it>, <it>t</it>}) time per pass. The problems find applications in VLSI physical design and in distributed systems.</p>
INDEX TERMS
Circuit and network partitioning, iterative improvement, NP-hard.
CITATION
Spyros Tragoudas, "Min-Cut Partitioning on Underlying Tree and Graph Structures", IEEE Transactions on Computers, vol.45, no. 4, pp. 470-474, April 1996, doi:10.1109/12.494104
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