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JanLung Sung, G. Robert Redinbo, "AlgorithmBased Fault Tolerant Synthesis for Linear Operations," IEEE Transactions on Computers, vol. 45, no. 4, pp. 425438, April, 1996.  
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@article{ 10.1109/12.494100, author = {JanLung Sung and G. Robert Redinbo}, title = {AlgorithmBased Fault Tolerant Synthesis for Linear Operations}, journal ={IEEE Transactions on Computers}, volume = {45}, number = {4}, issn = {00189340}, year = {1996}, pages = {425438}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.494100}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  AlgorithmBased Fault Tolerant Synthesis for Linear Operations IS  4 SN  00189340 SP425 EP438 EPD  425438 A1  JanLung Sung, A1  G. Robert Redinbo, PY  1996 KW  1fault detectable (1FD) system KW  algorithmbased fault tolerant (ABFT) synthesis KW  data flow graph (DFG) KW  fast Fourier transform (FFT) KW  gain matrix and error space. VL  45 JA  IEEE Transactions on Computers ER   
Abstract—Highlevel synthesis is becoming more important in practical design environments to meet new system requirements and, increasingly, fault tolerance is one especially because of highspeed and low power demands. This paper explores several basic aspects of lowcost fault tolerant synthesis for practical linear systems. It deals with practical design constraints that require basic operations to be only performed by a limited processing resources and do not normally assign each operation a separate processing resource. Two core issues, partitioning and allocation, for fault tolerant synthesis are examined. Results demonstrate a highlevel abstraction and framework for fault tolerant synthesis which is almost totally independent of the physical hardware implementation. Issues in designing 1fault detectable FFT system are considered in detail to illustrate the significance and effects of fault tolerant synthesis schemes. Our ultimate goal is to incorporate these techniques in future automated design tools so that fault tolerance features can be part of the design options.
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