Issue No.03 - March (1996 vol.45)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.485573
<p><b>Abstract</b>—A well-known scheme for obtaining high throughput adders is a pipeline in which each stage contains an array of half-adders performing a carry-save addition. This paper shows that other schemes can be designed, based on the idea of pipelining a serial-input adder or a ripple-carry adder. Such schemes offer a considerable savings of components while preserving high throughput. These schemes can be generalized by using (<it>p</it>, <it>q</it>) parallel counters to obtain pipelined adders for more than two numbers.</p>
Adders, high-speed adders, high-throughput adders, pipelined computation, skewed arithmetic.
Luigi Dadda, Vincenzo Piuri, "Pipelined Adders", IEEE Transactions on Computers, vol.45, no. 3, pp. 348-356, March 1996, doi:10.1109/12.485573