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Pipelined Adders
March 1996 (vol. 45 no. 3)
pp. 348-356

Abstract—A well-known scheme for obtaining high throughput adders is a pipeline in which each stage contains an array of half-adders performing a carry-save addition. This paper shows that other schemes can be designed, based on the idea of pipelining a serial-input adder or a ripple-carry adder. Such schemes offer a considerable savings of components while preserving high throughput. These schemes can be generalized by using (p, q) parallel counters to obtain pipelined adders for more than two numbers.

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Index Terms:
Adders, high-speed adders, high-throughput adders, pipelined computation, skewed arithmetic.
Citation:
Luigi Dadda, Vincenzo Piuri, "Pipelined Adders," IEEE Transactions on Computers, vol. 45, no. 3, pp. 348-356, March 1996, doi:10.1109/12.485573
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