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GF(2m) Multiplication and Division Over the Dual Basis
March 1996 (vol. 45 no. 3)
pp. 319-327

Abstract—In this paper an algorithm for GF(2m) multiplication/division is presented and a new, more generalized definition of duality is proposed. From these the bit-serial Berlekamp multiplier is derived and shown to be a specific case of a more general class of multipliers. Furthermore, it is shown that hardware efficient, bit-parallel dual basis multipliers can also be designed. These multipliers have a regular structure, are easily extended to different GF(2m) and hence suitable for VLSI implementations. As in the bit-serial case these bit-parallel multipliers can also be hardwired to carry out constant multiplication. These constant multipliers have reduced hardware requirements and are also simple to design. In addition, the multiplication/division algorithm also allows a bit-serial systolic finite field divider to be designed. This divider is modular, independent of the defining irreducible polynomial for the field, easily expanded to different GF(2m) and its longest delay path is independent of m.

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Index Terms:
Dual basis, finite field division, finite field multiplication, irreducible polynomials, Reed-Solomon codecs, systolic arrays, VLSI.
Sebastian T.J. Fenn, Mohammed Benaissa, David Taylor, "GF(2m) Multiplication and Division Over the Dual Basis," IEEE Transactions on Computers, vol. 45, no. 3, pp. 319-327, March 1996, doi:10.1109/12.485570
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