• Publication
  • 1996
  • Issue No. 3 - March
  • Abstract - A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach
 This Article 
 Bibliographic References 
 Add to: 
A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach
March 1996 (vol. 45 no. 3)
pp. 294-306

Abstract—This paper presents a method and an algorithm for generation of a parallel multiplier, which is optimized for speed. This method is applicable to any multiplier size and adaptable to any technology for which speed parameters are known. Most importantly, it is easy to incorporate this method in silicon compilation or logic synthesis tools. The parallel multiplier produced by the proposed method outperforms other schemes used for comparison in our experiment. It uses the minimal number of cells in the partial product reduction tree. These findings are tested on design examples simulated in 1μ CMOS ASIC technology.

[1] E. E. Swartzlander,Computer Arithmetic,, vol. 1. Los Alamitos, CA: IEEE Computer Society, 1990.
[2] K. Hwang,Computer Arithmetic, Principles, Architecture, and Design.New York: John Wiley&Sons, 1979.
[3] S.D. Pezaris,"A 40ns 17-bit Array Multiplier," IEEE Trans. Computers, vol. 20, no. 4, pp. 442-447, Apr. 1971.
[4] A.D. Booth,"A Signed Binary Multiplication Technique," Quarterly J. Mechanical Applications in Math., vol. 4, part 2, pp. 236-240, 1951.
[5] O.L. MacSorley,"High Speed Arithmetic in Binary Computers," IRE Proc., vol. 49, pp. 67-91, Jan. 1961.
[6] D. Villeger and V.G. Oklobdzija, “Evaluation of Booth Encoding Techniques for Parallel Multiplier Implementation,” Electronics Letters, vol. 29, no. 23, pp. 2,016-2,017, Nov. 1993.
[7] C.S. Wallace,"A Suggestion for a Fast Multiplier," IEEE Trans. Computers, vol. 13, no. 2, pp. 14-17, Feb. 1964.
[8] L. Dadda,"Some Schemes for Parallel Multipliers," Alta Frequenza, vol. 34, pp. 349-356, Mar. 1965.
[9] W.J. Stenzel,"A Compact High Speed Parallel Multiplication Scheme," IEEE Trans. Computers, vol. 26, no. 2, pp. 948-957, Feb. 1977.
[10] A. Weinberger,"4:2 Carry-Save Adder Module," IBM Technical Disclosure Bull., vol. 23, Jan. 1981.
[11] M.R. Santoro, "Design and Clocking of VLSI Multipliers," PhD dissertation, Technical Report no. CSL-TR-89-397, 1989.
[12] M.R. Santoro,"A Pipelined 64×64b Iterative Array Multiplier," Digest of Technical Papers, Int'l Solid-State Circuits Conf., Feb. 1988.
[13] M. Nagamatsu et al., "A 15nS 32×32-bit CMOS Multiplier with an Improved Parallel Structure," Digest of Technical Papers, IEEE Custom Integrated Circuits Conf., 1989.
[14] J. Mori et al., "A 10nS 54×54-b Parallel Structured Full Array Multiplier with 0.5-u CMOS Technology," IEEE J. Solid State Circuits, vol. 26, no. 4, Apr. 1991.
[15] P. Song and G. De Micheli, “Circuit and Architecture Trade-Offs for High-Speed Multiplication,” IEEE J. Solid State Circuits, vol. 26, no. 9, Sept. 1991.
[16] J. Fadavi-Ardekani, "M×N Booth Encoded Multiplier Generator Using Optimized Wallace Trees," IEEE Trans. VLSI Systems, June 1993, pp. 120-125.
[17] G. Bewick,"High Speed Multiplication," Proc. Electronic Research Laboratory Seminar, Stanford Univ., Mar.12, 1993 (also private communications).
[18] V.G. Oklobdzija and D. Villeger,"Multiplier Design Utilizing Improved Column Compression Tree and Optimized Final Adder in CMOS Technology," Proc. 10th Anniversary Symp. VLSI Circuits,Taipei, Taiwan, May 1993.
[19] T. Soulas,D. Villeger, and V.G. Oklobdzija,"An ASIC Multiplier for Complex Numbers," Proc. EURO-ASIC 93, The European Event in ASIC Design,Paris, France, Feb.22-25, 1993.
[20] D. Villeger,"Fast Parallel Multipliers," Final Report, Ecole Superieure d'Ingenieurs en Electrotechnique et Electronique,Noisy-le-Grand, France, May11, 1993.
[21] A.K.W. Yeung and R.K. Yu,"A Self-Timed Multiplier with Optimized Final Adder," Final Report for CS 292I (Prof. Oklobdzija), Univ. of California at Berkeley, Fall 1989.
[22] O.J. Bedrij,"Carry-Select Adder," IRE Trans. Electronic Computers, June 1962.
[23] V.G. Oklobdzija and E.R. Barnes,"On Implementing Addition in VLSI Technology," IEEE J. Parallel Processing and Distributed Computing, no. 5, 1988.
[24] B.D. Lee and V.G. Oklobdzija,"Delay Optimization of Carry-Lookahead Adder Structure," J. VLSI Signal Processing, vol. 3, no. 4, Nov. 1991.
[25] M. Suzuki et al., "A 1.5nS 32b CMOS ALU in Double Pass-Transistor Logic," Digest of Technical Papers, 1993 IEEE Solid-State Circuits Conf.,San Francisco, Feb.24-26, 1993.
[26] K. Fai-Pang et al., "Generation of High-Speed CMOS Multiplier-Accumulators," Proc. ICCD-88, Int'l Conf. Computer Design,Rye, N.Y., Oct. 1988.
[27] V.G. Oklobdzija,"Design and Analysis of fast Carry-Propagate Adder under Non-Equal Input Signal Arrival Profile," Proc. 28th Asilomar Conf. Signals, Systems, and Computers, Oct.30, 1994- Nov.2, 1994.
[28] K.J. Singh et al., "Timing Optimization of Combinational Logic," Proc. ICCAD 88, Int'l Conf. CAD, Nov. 1988.
[29] H.J. Touati, H. Savoj, and R.K. Brayton, "Delay Optimization of Combinational Logic Circuits by Clustering and Partial Collapsing," Proc. IEEE Conf. Computer-Aided Design, IEEE CS Press, 1991, pp. 188-191.
[30] 1.0-Micron Array-Based Products Databook, LSI Logic Corp., Sept. 1991.
[31] J.Y. Lee et al., "A High-Speed High-Density Silicon 8X8-bit Parallel Multiplier," IEEE J. Solid State Circuits, vol. 22, no. 1, Feb. 1987.
[32] Z. Wang,G.A. Julien, and W.C. Miller,"Column Compression Multipliers for Signal Processing Applications," VLSI Signal Processing.New York: IEEE Press, 1992.
[33] N. Okhubo et al., "A 4.4nS CMOS 54(54-b Multiplier Using Pass-Transistor Multiplexer," Proc. Custom Integrated Circuits Conf.,San Diego, Calif., May1-4, 1994.
[34] C. Martel,V.G. Oklobdzija,R. Ravi, and P. Stelling,"Design Strategies for Optimal Multiplier Circuits," Proc. 12th IEEE Symp. Computer Arithmetic,Bath, England, July19-21, 1995.

Index Terms:
Parallel multiplier, partial product reduction, Wallace tree, Dadda's counter, VLSI arithmetic, Booth encoding, 3:2 counter, 4:2 adder, array multiplier.
Vojin G. Oklobdzija, David Villeger, Simon S. Liu, "A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach," IEEE Transactions on Computers, vol. 45, no. 3, pp. 294-306, March 1996, doi:10.1109/12.485568
Usage of this product signifies your acceptance of the Terms of Use.