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| Vojin G. Oklobdzija, David Villeger, Simon S. Liu, "A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach," IEEE Transactions on Computers, vol. 45, no. 3, pp. 294-306, March, 1996. | |||
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| @article{ 10.1109/12.485568, author = {Vojin G. Oklobdzija and David Villeger and Simon S. Liu}, title = {A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach}, journal ={IEEE Transactions on Computers}, volume = {45}, number = {3}, issn = {0018-9340}, year = {1996}, pages = {294-306}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.485568}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
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| TY - JOUR JO - IEEE Transactions on Computers TI - A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach IS - 3 SN - 0018-9340 SP294 EP306 EPD - 294-306 A1 - Vojin G. Oklobdzija, A1 - David Villeger, A1 - Simon S. Liu, PY - 1996 KW - Parallel multiplier KW - partial product reduction KW - Wallace tree KW - Dadda's counter KW - VLSI arithmetic KW - Booth encoding KW - 3:2 counter KW - 4:2 adder KW - array multiplier. VL - 45 JA - IEEE Transactions on Computers ER - | |||
Abstract—This paper presents a method and an algorithm for generation of a parallel multiplier, which is optimized for speed. This method is applicable to any multiplier size and adaptable to any technology for which speed parameters are known. Most importantly, it is easy to incorporate this method in silicon compilation or logic synthesis tools. The parallel multiplier produced by the proposed method outperforms other schemes used for comparison in our experiment. It uses the minimal number of cells in the partial product reduction tree. These findings are tested on design examples simulated in 1μ CMOS ASIC technology.
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