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Issue No.03 - March (1996 vol.45)
pp: 270-277
ABSTRACT
<p><b>Abstract</b>—To develop better ROM BIST techniques we first experimentally surveyed cell faults, word-line faults, bit-line faults, delay faults and other types of faults occurring in 1,000 faulty mask ROM chips. We found that most of the stuck-at faults were within a single mat. We then theoretically analyzed the aliasing probability for a mask ROM containing a fault or faults within a single mat. To experimentally evaluate BIST aliasing errors we implemented six MISRs on a custom board and observed actual aliasing errors. The experimentally measured aliasing probabilities agreed with the probabilities derived theoretically. No aliasing error occurred for the 16-stage, 8-input MISR.</p>
INDEX TERMS
Built-in self-test, mask ROM, experimental faults analysis, aliasing probability, MISRs.
CITATION
Kazuhiko Iwasaki, Shigeo Nakamura, "Aliasing Error for a Mask ROM Built-In Self-Test", IEEE Transactions on Computers, vol.45, no. 3, pp. 270-277, March 1996, doi:10.1109/12.485566
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