Issue No.01 - January (1996 vol.45)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.481493
<p><b>Abstract</b>—This paper considers the problem of applying neural network for logic circuit testing and proposes an efficient method based on <it>hyperneural network</it> (HNN). The HNN uses an energy function that not only considers binary relations but also captures all higher order relations among <it>N</it> neurons. We illustrate the hyperneural concept using two formulations. First, a constraint engery function is defined and the gate model is obtained. Second, the Hopfield network is reformulated to generate the gate level hyperneural model. The gate level HNNs are used to give a mathematical form to the digital circuit that, in turn, requires optimization techniques to solve the test generation problem. We have used ISCAS'85 benchmark circuits to illustrate the method. Results are compared with those obtained from PODEM, MODEM, and FAN.</p>
Hyperneural model, logic circuit testing. neural network, NP-completeness, optimization, pseudo-Boolean programming, satisfiability problem.
Suresh Rai, Weian Deng, "Hyperneural Network-An Efficient Model for Test Generation in Digital Circuits", IEEE Transactions on Computers, vol.45, no. 1, pp. 115-121, January 1996, doi:10.1109/12.481493