Issue No.01 - January (1996 vol.45)
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/12.481489
<p><b>Abstract</b>—High observability testing environment allows internal circuit nodes to be used as test points. However, such flexibility requires the development of new ATPG algorithm. Previous reported algorithm does not guarantee full fault-coverage and assumes all internal circuit nodes are test points. The new algorithm described in this paper will generate a full fault-coverage test set for a fanout free combinational circuit. The main characteristic of the algorithm is that it generates test vectors as well as probe points. As a result, the probe points are different for each test vector, and the number of probe points is the minimum for test set generated. Results obtained show that an average of 30% test vector reduction is achieved compared with the conventional test method which uses only output pins as test points.</p>
Automatic test pattern generation, critical path tracing method, E-beam testing, fanout free combinational circuit, wafer stage testing.
Oliver Chiu-sing Choy, Lap-kong Chan, Ray Chan, Cheong F. Chan, "Test Generation with Dynamic Probe Points in High Observability Testing Environment", IEEE Transactions on Computers, vol.45, no. 1, pp. 88-96, January 1996, doi:10.1109/12.481489