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Test Generation with Dynamic Probe Points in High Observability Testing Environment
January 1996 (vol. 45 no. 1)
pp. 88-96

Abstract—High observability testing environment allows internal circuit nodes to be used as test points. However, such flexibility requires the development of new ATPG algorithm. Previous reported algorithm does not guarantee full fault-coverage and assumes all internal circuit nodes are test points. The new algorithm described in this paper will generate a full fault-coverage test set for a fanout free combinational circuit. The main characteristic of the algorithm is that it generates test vectors as well as probe points. As a result, the probe points are different for each test vector, and the number of probe points is the minimum for test set generated. Results obtained show that an average of 30% test vector reduction is achieved compared with the conventional test method which uses only output pins as test points.

[1] R. Kinch and C. Pottle,"Automatic test generation for electron-beam testing of VLSI circuits," Proc. IEEE ICCC, pp. 548-551, 1982.
[2] J. Mucha,"Bridging the gap between conventional e-beam testing," Microelectronic Eng., vol. 16, pp. 185-192, 1992.
[3] G. Swan,Y. Trivedi, and D. Wharton,"CrossCheck—A practical solution for ASIC testability," Proc. 1989 Int'l Test Conf., pp. 903-908, 1989.
[4] I. Kinch and J. Richard,"Automatic test generation for electron-beam testing of VLSI circuits," PhD thesis, School of Electrical Eng., Cornell Univ., Ithaca, N.Y., May 1982.
[5] M. Abramovici,P. Menon, and D. Miller,"Critical path tracing: An alternative to fault simulation," J. Design and Test of Computers, vol. 1, no. 1, pp. 83-93, 1984.
[6] P. Menon,Y. Levendel, and M. Abramovici,"Critical path tracing in sequential circuits," Proc. Int'l Conf. Computer-Aided Design, pp. 162-165, 1988.
[7] P. Menon,Y. Levendel, and M. Abramovici,"SCRIPT: A critical path tracing algorithm for synchronous sequential circuits," IEEE Trans. Computer-Aided Design, vol. 10, no. 6, 1991.
[8] D. Wang,"An algorithm for the generation of test sets for combinational logic network," IEEE Trans. Computers, vol. 24, no. 7, pp. 742-746, July 1975.
[9] M.W. Roberts and P.K. Lala,"Algorithm to detect reconvergent fanouts in logic circuits," IEE Proc., Part E, Computers and Digital Techniques, vol. 134, pp. 105-111, Mar. 1987.
[10] F. Brglez and H. Fujiwara,"A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran," Proc. IEEE Int'l Symp. Circuits Systems, 1985.

Index Terms:
Automatic test pattern generation, critical path tracing method, E-beam testing, fanout free combinational circuit, wafer stage testing.
Citation:
Oliver Chiu-sing Choy, Lap-kong Chan, Ray Chan, Cheong F. Chan, "Test Generation with Dynamic Probe Points in High Observability Testing Environment," IEEE Transactions on Computers, vol. 45, no. 1, pp. 88-96, Jan. 1996, doi:10.1109/12.481489
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