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Issue No.01 - January (1996 vol.45)
pp: 74-87
ABSTRACT
<p><b>Abstract</b>—A generally effective criterion for the selection of flip-flops in the partial scan problem for sequential circuit testability is to select flip-flops that break the cyclic structure of the circuit and reduce its sequential depth. The selection of flip-flops may also be subject to a prescribed bound on the clock period of the modified circuit (timing-driven partial scan). In this paper we propose two techniques (for non-timing-driven and timing-driven partial scan) which address the above criterion based on a transformation of sequential circuits known as retiming. For non-timing-driven partial scan, we employ retiming to rearrange the flip-flops of the circuit, so that its functionality is preserved, while the number of flip-flops that are needed to break all cycles and bound the sequential depth is significantly reduced. For timing-driven partial scan, we propose a retiming-based technique that reduces the overall area overhead required to achieve the clock period bound. Experimental results on the ISCAS'89 circuits show the benefit of our approach in both timing-driven and non-timing-driven partial scan.</p>
INDEX TERMS
Design for testability, minimum feedback vertex set, partial scan, retiming, sequential depth, timing-driven partial scan.
CITATION
Dimitrios Kagaris, Spyros Tragoudas, "Retiming-Based Partial Scan", IEEE Transactions on Computers, vol.45, no. 1, pp. 74-87, January 1996, doi:10.1109/12.481488
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