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| Sandeep K. Gupta, Dhiraj K. Pradhan, "Utilization of On-Line (Concurrent) Checkers during Built-In Self-Test and Vice Versa," IEEE Transactions on Computers, vol. 45, no. 1, pp. 63-73, January, 1996. | |||
| BibTex | x | ||
| @article{ 10.1109/12.481487, author = {Sandeep K. Gupta and Dhiraj K. Pradhan}, title = {Utilization of On-Line (Concurrent) Checkers during Built-In Self-Test and Vice Versa}, journal ={IEEE Transactions on Computers}, volume = {45}, number = {1}, issn = {0018-9340}, year = {1996}, pages = {63-73}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.481487}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Utilization of On-Line (Concurrent) Checkers during Built-In Self-Test and Vice Versa IS - 1 SN - 0018-9340 SP63 EP73 EPD - 63-73 A1 - Sandeep K. Gupta, A1 - Dhiraj K. Pradhan, PY - 1996 KW - Built-in self-test KW - BIST KW - concurrent checking KW - fault-escape probability KW - parity prediction. VL - 45 JA - IEEE Transactions on Computers ER - | |||
Abstract—Concurrent checkers are commonly used in computer systems to detect computational errors on-line, which enhances reliability. Using the coding theory framework developed earlier by the authors, it is shown in the following that concurrent checkers, already available within the circuit, can be utilized very effectively during off-line testing. Specifically, test time as well as fault escape probability can both be reduced simultaneously. The proposed combined scheme can be implemented with simple modification of existing hardware. Also shown is a novel use of BIST hardware for concurrent checking.
Specifically proposed is a novel, dual use of concurrent checkers and built-in self-test hardware, yielding mutual advantage.
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