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Irith Pomeranz, Sudhakar M. Reddy, "On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits," IEEE Transactions on Computers, vol. 45, no. 1, pp. 5062, January, 1996.  
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@article{ 10.1109/12.481486, author = {Irith Pomeranz and Sudhakar M. Reddy}, title = {On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits}, journal ={IEEE Transactions on Computers}, volume = {45}, number = {1}, issn = {00189340}, year = {1996}, pages = {5062}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.481486}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits IS  1 SN  00189340 SP50 EP62 EPD  5062 A1  Irith Pomeranz, A1  Sudhakar M. Reddy, PY  1996 KW  Lower bound on test set size KW  multipliers KW  path delay faults; KW  pipelining KW  resynthesis. VL  45 JA  IEEE Transactions on Computers ER   
Abstract—The problems involved in handling large numbers of path delay faults were alleviated in previous works, by developing fault simulation and test generation procedures that do not require paths to be explicitly considered. Thus, the methods developed allow the set of all path delay faults to be targeted during test generation and fault simulation. With the problems related to the number of paths removed, a new limiting factor in test generation for path delay faults is revealed, namely, the number of tests required to detect all path delay faults. In this work, the problems related to the number of tests are investigated. A procedure for computing a lower bound on the number of tests is described, and methods for synthesizing circuits with reduced lower bounds on the numbers of tests are developed. Experimental results are presented to demonstrate various aspects of the problem.
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