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On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits
January 1996 (vol. 45 no. 1)
pp. 50-62

Abstract—The problems involved in handling large numbers of path delay faults were alleviated in previous works, by developing fault simulation and test generation procedures that do not require paths to be explicitly considered. Thus, the methods developed allow the set of all path delay faults to be targeted during test generation and fault simulation. With the problems related to the number of paths removed, a new limiting factor in test generation for path delay faults is revealed, namely, the number of tests required to detect all path delay faults. In this work, the problems related to the number of tests are investigated. A procedure for computing a lower bound on the number of tests is described, and methods for synthesizing circuits with reduced lower bounds on the numbers of tests are developed. Experimental results are presented to demonstrate various aspects of the problem.

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Index Terms:
Lower bound on test set size, multipliers, path delay faults;,pipelining, resynthesis.
Citation:
Irith Pomeranz, Sudhakar M. Reddy, "On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits," IEEE Transactions on Computers, vol. 45, no. 1, pp. 50-62, Jan. 1996, doi:10.1109/12.481486
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