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Issue No.01 - January (1996 vol.45)
pp: 20-32
ABSTRACT
<p><b>Abstract</b>—We consider the removal of redundant logic from synchronous sequential circuits that have synchronizing sequences. The logic to be removed is identified by determining line stuck-at faults that do not affect the operation of the circuit. Such signal lines and some of the logic surrounding them can be removed without affecting the operation of the circuit. We show that circuits that have synchronizing sequences have certain properties that help in identifying logic that can be removed. Specifically, their state diagrams have a strongly connected component that contains all the synchronization states. This strongly connected component, called the main strongly -connected component, is reachable from all other strongly connected components. In addition to redundant faults that can always be removed, we show that there are two types of partially detectable faults in circuits that have synchronizing sequences. In the presence of the first type of faults, the circuit becomes unsynchronizable. Signal lines carrying such faults cannot be removed. The other type of partially detectable faults leave the circuit synchronizable. We show that such faults do not affect the main strongly connected component, and hence the corresponding signal lines can be removed without affecting the operation of the circuit after it is synchronized. We also define weakly synchronizable circuits and derive similar results regarding the removal of redundant logic in them. The class of removable lines is thus extended beyond those corresponding to redundant faults to include some partially detectable faults as well. We present experimental evidence to the existence of partially detectable faults that correspond to signal lines that can be removed in benchmark circuits.</p>
INDEX TERMS
Fault removal, partially detectable faults, redundancy removal, redundant faults, synchronous sequential circuits, synchronizing sequences.
CITATION
Irith Pomeranz, "On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences", IEEE Transactions on Computers, vol.45, no. 1, pp. 20-32, January 1996, doi:10.1109/12.481483
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