This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
The Performance of Counter- and Correlation-Based Schemes for Branch Target Buffers
December 1995 (vol. 44 no. 12)
pp. 1383-1393

AbstractBranch target buffers, or BTBs, can be used to improve CPU performance by maintaining target and history information of previously executed branches. We present trace-driven simulation results comparing counter-based and correlation-based prediction schemes for a variety of branch target buffer sizes. We report relative performance estimates to show both the relative merits of various techniques and their effects on performance for current microprocessors. Our results indicate that counter-based schemes outperform correlation-based schemes for small buffers, but that the opposite becomes true as buffer size increases. This is due to the importance of hit ratio over prediction success in branch target buffer design. The transition point between counter- and correlation-based schemes is dependent on the size of the working set of dynamic branches for a given collection of benchmark programs.

Our results also show that for small BTBs, hit ratio and hence performance decrease as the number of correlation bits increase. This is due to non-random distribution of correlation vectors causing increased collisions for BTB locations. Only when a BTB becomes large enough to capture the working set of a program’s branch and correlation vector references do the expected benefits of correlation-based schemes manifest themselves.

[1] S. McFarling and J. Hennessy, “Reducing the Cost of Branches,” Proc. 13th Ann. Int'l Symp. Computer Architecture, June 1986.
[2] B. Bray and M. Flynn,“Strategies for branch target buffers,” Proc. 24th Int’l Symp. Microarchitecture, pp 42-50,Albuquerque, N.M., 1991.
[3] E. McLellan, "The Alpha AXP Architecture and 21064 Processor," IEEE Micro, vol. 13, no. 3, pp. 36-47, June 1993.
[4] D. Poplawski,“Low cost branch prediction,” Proc. 23rd Ann. Allerton Conf. Comm., Control, and Computing, pp 979-983, Oct. 1985.
[5] J. Fisher and S. Freudenberger,"Predicting Conditional Branch Directions from Previous Runs of a Program," Proc. 5th Int'l Conf. Architectural Support for Programming Languages and Operating Systems (ASPLOS-V), ACM Press, 1992, pp. 85-95.
[6] J.E. Smith, "A Study of Branch Prediction Strategies," Proc. Eighth Ann. Int'l Symp. Computer Architecture, pp. 135-148, June 1981.
[7] J.L. Hennessy and D.A. Patterson, Computer Architecture: A Quantitative Approach, Morgan Kaufmann, San Mateo, Calif., 1990.
[8] W.W. Hwu, T.M. Conte, and P.P. Chang, "Comparing Software and Hardware Schemes for Reducing the Cost of Branches," Proc. 16th Ann. Int'l Symp. Computer Architecture, 1989.
[9] T.Y. Yeh and Y.N. Patt,"Alternative Implementations of Two-Level Adaptive Training Branch Prediction," Proc. 19th Ann. Int'l Symp. Computer Architecture, pp. 124-134, 1992.
[10] S. Pan, K. So, and J. Rahmeh, “Improving the Accuracy of Dynamic Branch Prediction Using Branch Correlation,” Proc. Fifth Int'l Conf. Architectural Support for Programming Languages and Operating Systems, pp. 76-84, Oct. 1992.
[11] C.H. Perleberg and A.J. Smith, "Branch Target Buffer Design and Optimization," IEEE Trans. Computers, vol. 42, no. 4, pp. 396-412, Apr. 1993.
[12] T. Keller,“SPEC benchmarks and competitive results,” Performance Evaluation Review, vol. 18, no. 3, pp. 19-20, Nov. 1990.
[13] D.N. Pnevmatikatos and M.D. Hill,“Cache performance on the integer SPEC benchmarks,” Computer Architecture News, vol. 18, no. 2, pp. 53-68, June 1990.
[14] M.D. Smith,“Tracing with pixie,” Technical Report CSL-TR-91-497, Stanford Univ., Nov. 1991.
[15] A. Mital,“Branch prediction strategies and their effect on superscalar processors,” Master’s Thesis, Thayer School of Eng., Dartmouth College, June 1993.
[16] D.R. Kaeli and P.G. Emma, "Branch History Table Prediction of Moving Target Branches Due to Subroutine Returns," Proc. 18th Int'l Symp. Computer Architecture, pp. 34-42,Toronto, May 1991.
[17] H.G. Cragon, Branch Strategy Taxonomy and Performance, IEEE CS Press, Los Alamitos, Calif., 1991.
[18] M.D. Hill, "A Case for Direct-Mapped Caches," Computer, Dec. 1988.

Index Terms:
Branch correlation, branch prediction, branch target buffer, performance modeling, trace-driven simulation.
Citation:
Amit Mital, Barry Fagin, "The Performance of Counter- and Correlation-Based Schemes for Branch Target Buffers," IEEE Transactions on Computers, vol. 44, no. 12, pp. 1383-1393, Dec. 1995, doi:10.1109/12.477244
Usage of this product signifies your acceptance of the Terms of Use.