
This Article  
 
Share  
Bibliographic References  
Add to:  
Digg Furl Spurl Blink Simpy Del.icio.us Y!MyWeb  
Search  
 
ASCII Text  x  
David M. Mandelbaum, "Division Using a LogarithmicExponential Transform to Form a Short Reciprocal," IEEE Transactions on Computers, vol. 44, no. 11, pp. 13261330, November, 1995.  
BibTex  x  
@article{ 10.1109/12.475129, author = {David M. Mandelbaum}, title = {Division Using a LogarithmicExponential Transform to Form a Short Reciprocal}, journal ={IEEE Transactions on Computers}, volume = {44}, number = {11}, issn = {00189340}, year = {1995}, pages = {13261330}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.475129}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Division Using a LogarithmicExponential Transform to Form a Short Reciprocal IS  11 SN  00189340 SP1326 EP1330 EPD  13261330 A1  David M. Mandelbaum, PY  1995 KW  Array KW  division KW  exponential KW  logarithm KW  reciprocation KW  tree. VL  44 JA  IEEE Transactions on Computers ER   
[1] R. Stefanelli,“A suggestion for a high speed parallel binary divider,” IEEE Trans. Computers, vol. 21, pp. 4245, Jan. 1972.
[2] D.M. Mandelbaum,“A systematic method for division with high average bit skipping,” IEEE Trans. Computers, vol. 39, pp. 127130, Jan. 1990.
[3] D.M. Mandelbaum,“Some results on a SRT type division scheme,” IEEE Trans. Computers, vol. 42, pp. 102106, Jan. 1993.
[4] E.M. Schwarz and M.J. Flynn,“Cost efficient high radix division,” J. VLSI Signal Processing, pp. 293305, Aug. 1991.
[5] E.M. Schwarz and M.J. Flynn,“Hardware starting approximation for the square root operation,” Proc. IEEE 11th Symp. Computer Arithmetic, pp. 10311, 1993.
[6] E.M. Schwarz and M.J. Flynn,“Parallel high radix nonrestoring division,” IEEE Trans. Computers, vol. 42, no. 10, pp. 1,2341,246, Oct. 1993.
[7] D. Wong and M. Flynn,“Fast division using accurate quotient approximations to reduce the number of iterations,” IEEE Trans. Computers, vol. 41, pp. 981995, Aug. 1992.
[8] S. Waser and M.J. Flynn,Introduction to Arithmetic for Digital System Designers.New York: CBS College Publishing, 1982.
[9] D. Knuth, The Art of Computer Programming, Vol. 2, AddisonWesley, Reading, Mass., 1998.
[10] J.N. Mitchell Jr.,“Computer multiplication and division using binary logarithm,” IRE Trans. Electronic Computers, vol. 11, pp. 512517, Aug. 1962.
[11] C.S. Wallace,“A suggestion for a fast multiplier,” IEEE Trans. Electronic Computers, vol. 13, pp. 1417, Feb. 1964.
[12] L. Dadda,“Some schemes for parallel multipliers,” Alta Frequenza, vol. 34, pp. 349356, May 1965.
[13] S.D. Pezaris,“A 40 ns 17 bit by 17 bit array multiplier,” IEEE Trans. Computers, vol. 20, pp. 442447, Apr. 1971.
[14] A. Avizienis,“Signed digit number representations for fast parallel arithmetic,” IEEE Trans. Computers, vol. 10, pp. 389400, 1961.
[15] K. Hwang,Computer Arithmetic, Principles, Architecture, and Design.New York: John Wiley&Sons, 1979.
[16] E.E. Swartzlander Jr., and A.G. Alexopoulos,“The sign/logarithm number system,” IEEE Trans. Computers, vol. 24, pp. 1,2381,242, Dec. 1975.
[17] W.S. Briggs and D.W. Matula, "A 17×69 Bit Multiply and Add Unit with Redundant Binary Feedback and Single Cycle Latency," Proc. 11th Symp. Computer Arithmetic, pp. 163170, 1993.
[18] M.D. Ercegovac and T. Lang,“Simple radix4 division with operands scaling,” IEEE Trans. Computers, vol. 39, no. 9, pp. 1,2041,207, Sept. 1990.
[19] E.V. Krishnamurthy,“On rangetransformation techniques for division,” IEEE Trans. Computers, vol. 19, no. 2, pp. 157160, Feb. 1970.
[20] E.V. Krishnamurthy,“A more efficient rangetransformation algorithm for signeddigit division,” Int’l J. Control, vol. 12, no. 1, pp. 7379, 1970.
[21] D.W. Matula,“Design of a highly parallel IEEE floating point arithmetic unit,” Symp. Combinatorial Optimization Science and Technology (COST) at RUTCOR/DIMACS, Apr. 1991.
[22] D.D. Sarma and D.W. Matula,“Measuring the accuracy of ROM reciprocal tables,” Proc. IEEE 11th Symp. Computer Arithmetic, pp. 95102,Windsor, Canada, 1993.
[23] A. Svoboda,“An algorithm for division,” Information Proc. Machines, no. 9, pp. 2534, 1963.
[24] N. Takagi,H. Yasuura,, and S. Yajima,“Highspeed VLSI multiplication algorithm with a redundant binary addition tree,” IEEE Trans. Computers, vol. 34, no. 9, pp. 789796, Sept. 1985.
[25] S.F. Anderson,J.G. Earle,R.E. Goldschmidt,, and D.M. Powers,“The IBM system/360 model 91: Floating point execution unit,” IBM J. Research and Development, vol. 11, no. 1, pp. 3453, Jan. 1967.
[26] E.M. Schwarz,“Highradix algorithms for highorder arithmetic expressions,” doctorial dissertation, Stanford Univ., Jan. 1993.