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Issue No.11 - November (1995 vol.44)
pp: 1283-1295
ABSTRACT
<p><it>Abstract</it>—When using built-in self-test (BIST) for testing VLSI circuits the circuit response to an input test sequence, which may consist of thousands to millions of bits, is <it>compacted</it> into a <it>signature</it> which consists of only tens of bits. Usually a linear feedback shift register (LFSR) is used for response compaction via polynomial division. The compacting function is a <it>many-to-one</it> function and as a result some erroneous responses may be mapped to the same signature as the good response. This is known as <it>aliasing</it>.</p><p>In this paper we deal with the selection of a feedback polynomial for the compacting LFSR, such that an erroneous response resulting from any <it>modeled fault</it> is mapped to a signature that is different from that for the good response. Such LFSRs are called <it>zero-aliasing</it> LFSRs. Only zero-aliasing LFSRs with primitive or irreducible feedback polynomials are considered due to their suitability for BIST test pattern generation.</p><p>Upper bounds are derived for the least degree irreducible and primitive zero-aliasing LFSR polynomials. These bounds show that in all practical test applications such a polynomial will be of degree less than 53. Expected bounds are derived and show that when the number of faults is less than 10<super>6</super>, then this degree is at most 21.</p><p>Procedures to find irreducible and primitive zero-aliasing LFSR polynomials of: 1) the smallest degree and 2) a pre-specified degree; are presented. A low-complexity procedure to find a zero-aliasing LFSR polynomial is also presented. The worst case as well as expected time complexities of all these procedures are derived. Experimental results are presented for practical problem sizes to demonstrate the applicability of the proposed procedures.</p>
INDEX TERMS
Built-in self-test, linear feedback shift registers, response compaction, signature analysis, zero-aliasing.
CITATION
Sandeep K. Gupta, "Zero-Aliasing for Modeled Faults", IEEE Transactions on Computers, vol.44, no. 11, pp. 1283-1295, November 1995, doi:10.1109/12.475124
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