This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Zero-Aliasing for Modeled Faults
November 1995 (vol. 44 no. 11)
pp. 1283-1295

Abstract—When using built-in self-test (BIST) for testing VLSI circuits the circuit response to an input test sequence, which may consist of thousands to millions of bits, is compacted into a signature which consists of only tens of bits. Usually a linear feedback shift register (LFSR) is used for response compaction via polynomial division. The compacting function is a many-to-one function and as a result some erroneous responses may be mapped to the same signature as the good response. This is known as aliasing.

In this paper we deal with the selection of a feedback polynomial for the compacting LFSR, such that an erroneous response resulting from any modeled fault is mapped to a signature that is different from that for the good response. Such LFSRs are called zero-aliasing LFSRs. Only zero-aliasing LFSRs with primitive or irreducible feedback polynomials are considered due to their suitability for BIST test pattern generation.

Upper bounds are derived for the least degree irreducible and primitive zero-aliasing LFSR polynomials. These bounds show that in all practical test applications such a polynomial will be of degree less than 53. Expected bounds are derived and show that when the number of faults is less than 106, then this degree is at most 21.

Procedures to find irreducible and primitive zero-aliasing LFSR polynomials of: 1) the smallest degree and 2) a pre-specified degree; are presented. A low-complexity procedure to find a zero-aliasing LFSR polynomial is also presented. The worst case as well as expected time complexities of all these procedures are derived. Experimental results are presented for practical problem sizes to demonstrate the applicability of the proposed procedures.

[1] A.V. Aho,J.E. Hopcroft, and J.D. Ullman,The Design and Analysis of Computer Algorithms.Reading, Mass.: Addison-Wesley, 1974.
[2] R.K. Brayton, G.D. Hachtel, C.T. McMullen, and A.L. Sangiovanni-Vincintelli, Logic Minimization Algorithms for VLSI Synthesis.Boston: Kluwer Academic, 1984.
[3] E.R. Berlekamp,“Factoring polynomials over large finite fields,” Mathematics of Computation, vol. 24, no. 111, pp. 713-735, July 1970.
[4] D.G. Cantor and H. Zassenhaus,“A new algorithm for factoring polynomials over finite fields,” Mathematics of Computation, vol. 36, no. 154, pp. 587-592, Apr. 1981.
[5] K. Chakrabarty and J.P. Hayes, "Aliasing-Free Error Detection (ALFRED)," Proc. 1993 VLSI Test Symp., pp. 260-267, Apr. 1993.
[6] T.H. Cormen,C.E. Leiserson, and R.L. Rivest,Introduction to Algorithms.Cambridge, Mass.: MIT Press/McGraw-Hill, 1990.
[7] S. Gupta, D.K. Pradhan, and S.M. Reddy, "Zero Aliasing Compression," Proc. IEEE Int'l Symp. Fault-Tolerant Computing, pp. 254-263, June 1990.
[8] R. L. Graham, D. E. Knuth, and O. Patashnik,Concrete Mathematics. Reading, MA: Addison-Wesley, 1989.
[9] D.R. Heath-Brown,“Zero-free regions for Dirichlet L-functions, and the least prime in anarithmetic progression,” Proc. London Math. Soc., vol. 64, no. 3, pp. 265-338, 1992.
[10] A. Lempel,G. Seroussi,, and S. Winograd,“Complexity of multiplication in finite fields,” Theoretical Computer Science, vol. 22, pp. 285-296, 1983.
[11] M. Lempel,S.K. Gupta,, and M.A. Breuer,“Test embedding with discrete logarithms,” Proc. 12th IEEE VLSI Test Symp., pp. 74-80, 1994.
[12] R. Lidl and H. Niederreiter,An Introduction to Finite Fields and Their Applications.Cambridge: Cambridge Univ. Press, 1986.
[13] I. Pomeranz,S.M. Reddy,, and R. Tangirala,“On achieving zero aliasing for modeled faults,” Proc. European Design Automation Conf., 1992.
[14] D.K. Pradhan and S. Gupta, A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression IEEE Trans. Computers, vol. 40, no. 6, June 1991.
[15] M.O. Rabin,“Probabilistic algorithms in finite fields,” SIAM J. Computing, vol. 9, no. 2, pp. 273-280, May 1980.
[16] P. Ribenboim,The Book of Prime Number Records, 2nd Edition. Springer-Verlag, 1989.
[17] A. Schönhage,“Schnelle Multiplikation von Polynomenüber Körpern der Charakteristik 2,” Acta Informatica, vol. 7, pp. 395-398, 1977.

Index Terms:
Built-in self-test, linear feedback shift registers, response compaction, signature analysis, zero-aliasing.
Citation:
Sandeep K. Gupta, Mody Lempel, "Zero-Aliasing for Modeled Faults," IEEE Transactions on Computers, vol. 44, no. 11, pp. 1283-1295, Nov. 1995, doi:10.1109/12.475124
Usage of this product signifies your acceptance of the Terms of Use.