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Issue No.09 - September (1995 vol.44)
pp: 1121-1130
ABSTRACT
<p><it>Abstract</it>—In this work, the design of a Galois enhanced quadratic residue number system (GEQRNS) [<ref rid="BIBC11219" type="bib">9</ref>], [<ref rid="BIBC11217" type="bib">7</ref>] processor is presented, which can be used to construct linear systolic arrays. The processor architecture has been optimized to perform multiply-accumulate type operations on complex operands. The properties of finite fields have been exploited to perform this complex multiplication in a manner which results in greatly reduced hardware complexity. The processor is also shown to have a high degree of tolerance to manufacturing defects and faults which can occur during operation. The combination of these two factors makes this an ideal candidate for array signal processing applications, where high complex arithmetic data rates are required. A prototype processing element has been fabricated in 1.5 μm CMOS technology, which is shown to operate at 40 MHz.</p>
INDEX TERMS
Fault-tolerant, residue number system (RNS), systolic array, DSP, yield enhancement, redundancy, VLSI design.
CITATION
Fred J. Taylor, Jeremy C. Smith, "A Fault-Tolerant GEQRNS Processing Element for Linear Systolic Array DSP Applications", IEEE Transactions on Computers, vol.44, no. 9, pp. 1121-1130, September 1995, doi:10.1109/12.464390
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