|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
| | ||
| Search | ||
| ||
| ASCII Text | x | ||
| G. Sourtziotis, V. V. Dimakopoulos, A. Paschalis, D. Nikolos, "On TSC Checkers for m-out-of-n Codes," IEEE Transactions on Computers, vol. 44, no. 8, pp. 1055-1059, August, 1995. | |||
| BibTex | x | ||
| @article{ 10.1109/12.403723, author = {G. Sourtziotis and V. V. Dimakopoulos and A. Paschalis and D. Nikolos}, title = {On TSC Checkers for m-out-of-n Codes}, journal ={IEEE Transactions on Computers}, volume = {44}, number = {8}, issn = {0018-9340}, year = {1995}, pages = {1055-1059}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.403723}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - On TSC Checkers for m-out-of-n Codes IS - 8 SN - 0018-9340 SP1055 EP1059 EPD - 1055-1059 A1 - G. Sourtziotis, A1 - V. V. Dimakopoulos, A1 - A. Paschalis, A1 - D. Nikolos, PY - 1995 KW - Fault detection KW - fault tolerance KW - MOS transistor implementation KW - m-out-of-n code KW - totally self-checking checkers. VL - 44 JA - IEEE Transactions on Computers ER - | |||
[1] W.C. Carter and P.R. Schneider,“Design of dynamically checked computers,” Proc. IFIP’68, vol. 2, pp. 878-883,Edinburgh, 1968.
[2] D.A. Anderson and G. Metze,“Design of totally self-checking check circuits for m-out-of-n codes,” IEEE Trans. Computers, vol. 22, pp. 263-269, Mar. 1973.
[3] S.M. Reddy,“A note on self-checking checkers,” IEEE Trans. Computers, vol. 23, pp. 1,100-1,102, Oct. 1974.
[4] J.E. Smith,“The design of totally self-checking check circuits for a class of unordered codes,” J. Design Automation Fault-Tolerant Computing, vol. 2, pp. 321-342, Oct. 1977.
[5] M.A. Marouf and A.D. Friedman,“Efficient design of self-checking checkers for any m-out-of-n code,” IEEE Trans. Computers, vol. 27, pp. 482-490, June 1978.
[6] N. Gaitanis and C. Halatsis,“A new design method for m-out-of-n TSC checkers,” IEEE Trans. Computers, vol. 32, pp. 273-283, Mar. 1983.
[7] C. Efstathiou and C. Halatsis,“Modular realization of totally self-checking checkers for m-out-of-n codes,” Proc. 13th FTCS,Milan, pp. 154-161, June 1983.
[8] S. Piestrak,“Design method of totally self-checking checkers for m-out-of-n codes,” Proc. 13th FTCS,Milan, pp. 162-168, June 1983.
[9] T. Nanya and Y. Tohma,“A 3-level realization of totally self-checking checkers for m-out-of-n codes,” Proc. 13th FTCS,Milan, pp. 173-176, June 1983.
[10] N. Jha and A. Abraham,“Techniques for efficient MOS implementation of totally self-checking checkers,” Proc. 15th FTCS, pp. 430-435, June 1985.
[11] C. Efstathiou and C. Halatsis,“Efficient modular design of m-out-of-2m TSC checkers, for m = 2k−1, k>2,” Electronics Letters, vol. 21, pp. 1,083-1,084, Nov. 1985.
[12] A.M. Paschalis et al., “Efficient Modular Design of TSC Checkers form-out-of-nCodes,” IEEE Trans. Computers, vol. 37, no. 3, pp. 301-309, Mar. 1988.
[13] S.J. Piestrak,"The Minimal Test Set for Sorting Networks and the Use of Sorting Networks in Self-Testing Checkers for Unordered Codes," Digest of Papers 20th Int'l FTC Symp., Newcastle upon Tyne, U.K. pp. 457-464, June 1990.
[14] C.H. Sequin,“Managing VLSI complexity: An outlook,” Proc. IEEE, vol. 71, no 1, pp. 149-166, Jan. 1983.
[15] D.A. Anderson,“Design of self-checking digital networks using coding techniques,” Coordinated Science Lab., Rep. R-527, Univ. of Illi nois, Oct. 1971.
[16] M.A. Marouf and A.D. Friedman,“Design of self-checking checkers for Berger codes,” Proc. Eighth FTCS, pp. 179-184, June 1978.
[17] M. Annaratone,Digital CMOS Circuit Design. Kluwer Academic Publishers, 1986.
[18] V. Dimakopoulos and G. Sourtziotis,“Design of TSC circuits for m-out-of-n codes in VLSI MOS technology,” Diploma thesis (in Greek), Dept. of Computer Eng. and Informatics,Univ. of Patras, 1990.

