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A Multiple-Valued Reed-Muller Transform for Incompletely Specified Functions
August 1995 (vol. 44 no. 8)
pp. 1012-1020

Abstract—This paper considers the Reed-Muller transform for incompletely specified multiple-valued logic functions, which is obtained as the finite field polynomial representation. A new algorithm for dealing with single-variable functions is presented. It is applicable to finite fields of small sizes (two to four), which is of interest because only these fields are readily implementable with today’s MVL technology. It is shown how such or any similar single-variable algorithm can be used to obtain a fast n-variable Reed-Muller transform. Based on this transform, a heuristic scheme is derived for dealing with incompletely specified functions. It has better computational properties than other methods and achieves the best results when applied to functions with a large number of unspecified points.

[1] A.E.A. Almaini,P. Thompson,, and D. Hanson,“Tabular techniques for Reed-Muller logic,” Int’l J. Electronics, vol. 70, no. 1, pp. 23-34, Jan. 1991.
[2] P.W. Besslich,“Efficient computer method for ExOR logic design,” IEE Proc., Part E, vol. 130, no. 6, pp. 203-206, Nov. 1983.
[3] S.D. Brown,R.J. Francis,J. Rose,, and Z.G. Vranesic,Field-Programmable Gate Arrays. Kluwer Academic Publishers, 1992.
[4] J. Boyar,G. Frandsen,, and C. Sturtivant,“An arithmetic model of computation equivalent to threshold circuits,” Theoretical Computer Science, vol. 9303-319, May 1992.
[5] M. Davio,J.-P. Deschamps,, and A. Thayse,Discrete and Switching Functions.New York: McGraw-Hill, 1978.
[6] T. Damarla,“Generalized transforms for multiple valued circuits and their fault detection,” IEEE Trans. Computers, vol. 41, no. 9, pp. 1,101-1,109, Sept. 1992.
[7] D.H. Green and I.S. Taylor,“Modular representation of multiple-valued logic systems,” IEE Proc., Part E, vol. 121, no. 6, pp. 409-418, June 1974.
[8] D.H. Green and I.S. Taylor,“Multiple-valued switching circuit design by means of generalized Reed-Muller expansions,” Digital Processes, vol. 2, pp. 63-81, 1976.
[9] D.H. Green,“Reed-Muller expansions of incompletely specified functions,” IEE Proc., Part E, vol. 134, no. 5, pp. 228-236, Sept. 1987.
[10] D.H. Green,“Reed-Muller expansions with fixed and mixed polarities over GF(4),” IEE Proc., Part E, vol. 137, no. 5, pp. 380-388, Sept. 1990.
[11] M.G. Karpovsky, ed., Spectral Techniques and Fault Detection.Orlando, Fla.: Academic Press, 1985.
[12] P.K. Lui and J.C. Muzio,“Boolean matrix transforms for the minimization of modulo-2 canonical expansions,” IEEE Trans. Computers, vol. 41, no. 3, pp. 343-347, Mar. 1992.
[13] L. McKenzie,A.E.A. Almaini,J.F. Miller,, and P. Thompson,“Optimization of Reed-Muller logic functions,” Int’l J. Electronics, vol. 75, no. 3, pp. 451-466, Sept. 1993.
[14] K.S. Menger, Jr.,“A transform for logic networks,” IEEE Trans. Computers, vol. 18, no. 3, pp. 241-251, Mar. 1969.
[15] D.K. Pradhan,“A theory of Galois switching functions,” IEEE Trans. Computers, vol. 27, no. 3, pp. 239-247, Mar. 1978.
[16] M.W. Riege and P.W. Besslich,“Low-complexity synthesis of incompletely specified multiple-output mod-2 sums,” IEE Proc., Part E, vol. 139, no. 4, pp. 355-362, July 1992.
[17] T. Sasao,“And-Exor expressions and their optimization,” Logic Synthesis and Optimization, T. Sasao, ed., pp. 287-312, Kluwer Academic Publishers, 1993.
[18] T. Sasao and P. Besslich, “On the Complexity of mod-2 Sum PLA's,” IEEE Trans. Computers, vol. 39, no. 2, pp. 262-266, Feb. 1990.
[19] D. Varma and E.A. Trachtenberg,“Design automation tools for efficient implementation of logic functions by decomposition,” IEEE Trans. Computer-Aided Design, vol. 8, no. 8, pp. 901- 916, Aug. 1989.
[20] D. Varma and E.A. Trachtenberg,“Computation of Reed-Muller expansions of incompletely specified Boolean functions from reduced representations,” IEE Proc., Part E, vol. 138, no. 2, pp. 85-92, Mar. 1991.
[21] D. Varma and E.A. Trachtenberg,“Efficient spectral methods for logic synthesis,” Logic Synthesis and Optimization, T. Sasao, ed., pp. 215-232, Kluwer Academic Publishers, 1993.
[22] T.C. Wesselkamper,“Divided difference method for Galois switching functions,” IEEE Trans. Computers, vol. 27, no. 3, pp. 232-238, Mar. 1978.
[23] Xilinx,EPLD - PAL Conversion Guide.San Jose, Calif.: Xilinx, Inc., 1993.
[24] Z. Zilic and Z. Vranesic,“Current mode CMOS Galois field circuits,” Proc. 23rd Int’l Symp. Multiple-Valued Logic, pp. 245-250, May 1993.

Index Terms:
Multiple-valued logic, Reed-Muller transform, incompletely specified functions, synthesis of logic functions, finite fields.
Zvonko G. Vranesic, Zeljko Zilic, "A Multiple-Valued Reed-Muller Transform for Incompletely Specified Functions," IEEE Transactions on Computers, vol. 44, no. 8, pp. 1012-1020, Aug. 1995, doi:10.1109/12.403717
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