This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Application of Bipartite Graphs for Achieving Race-Free State Assignments
August 1995 (vol. 44 no. 8)
pp. 1002-1011

Abstract—Achieving race-free state assignments is an important objective in the synthesis of asynchronous sequential logic circuits (ASLCs). Traditionally, adjacency diagrams are used to help identify and resolve race conditions; however, this approach has a high degree of computational complexity. This paper presents an efficient state assignment algorithm that utilizes a pattern matching technique to predict races and to eliminate the need for enumerative searches. More specifically, the race-free state assignment problem is formulated as the embedding of a bipartite connected graph onto an n-cube and achieves a near minimum number of state variables. This algorithm has been evaluated using several representative examples. Results show that the developed algorithm provides better performance than existing algorithms. Due to the simplicity of the bipartite representation of an n-cube, the developed algorithm is suitable for ASLC synthesis that may involve a relatively large number of states.

[1] S.H. Unger, Asynchronous Sequential Switching Circuits.New York: Wiley-Interscience, 1969.
[2] J.F. Wakerly,Digital Design Principles and Practices.Englewood Cliffs, N.J.: Prentice Hall, 1990.
[3] K.J. Breeding,Digital Design Fundamentals.Englewood Cliffs, N.J.: Prentice Hall, 1989.
[4] D.L. Dietmeyer,Logic Design of Digital Systems, 3rd ed. Boston: Allyn and Bacon, Inc., 1988.
[5] A.D. Friedman,Fundamentals of Logic Design and Switching Theory.Rockville, Md.: Computer Science Press, Inc., 1986.
[6] E.J. McCluskey,Logic Design Principles.Englewood Cliffs, N.J.: Prentice Hall, 1986.
[7] J.-W. Kang,P.D. Fisher,, and C.-L. Wey,“An efficient modeling and synthesis procedure of asynchronoussequential logic circuits,” IEE Proc.: Computers and Digital Techniques, vol. 141, no. 1, pp. 61-64, Jan. 1994.
[8] J.-W. Kang,C.-L. Wey,, and P.D. Fisher,“An efficient modeling and synthesis procedure of asynchronoussequential logic circuits,” Proc. 35th Midwest Symp. Circuits and Systems, vol. 1, pp. 512-515, Aug. 1992.
[9] G. Saucier,“State assignment of asynchronous sequential machines using graphtechniques,” IEEE Trans. Computers, vol. 21, no. 3, pp. 282-288, Mar. 1972.
[10] F. Harary,Graph Theory.Reading, Mass.: Addison-Wesley, 1969.
[11] S. Foldes,“A characterization of hypercubes,” Discrete Mathematics, vol. 17, pp. 155-159, 1977.
[12] J.-W. Kang,“The modeling and synthesis of asynchronous sequential logiccircuits,” PhD dissertation, Dept. of Electrical Eng., Michigan State Univ., 1993.
[13] P.D. Fisher and S.-F. Wu,“Race-free state assignments for synthesizing large-scaleasynchronous sequential logic circuits,” IEEE Trans. Computers, vol. 42, no. 9, pp. 1,025-1,034, Sept. 1993.
[14] J.-W. Kang,C.-L. Wey,, and P.D. Fisher,“A synthesis procedure for large scale finite state machines,” Proc. 36th Midwest Symp. Circuits and Systems, vol. 2, pp. 1,304-1,307, Aug. 1993.
[15] Logic Synthesis and Optimization Benchmarks, User Guide. Microelectronics Research Center of North Carolina, 1988.

Index Terms:
Asynchronous sequential logic circuits, adjacency diagram, bipartite adjacency table, bipartite graph, bipartite representation of an n-cube, mapping, partitioning, race-free state assignments, state assignments algorithm.
Citation:
Chin-Long Wey, Jun-Woo Kang, P. David Fisher, "Application of Bipartite Graphs for Achieving Race-Free State Assignments," IEEE Transactions on Computers, vol. 44, no. 8, pp. 1002-1011, Aug. 1995, doi:10.1109/12.403716
Usage of this product signifies your acceptance of the Terms of Use.