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Efficient Stack Simulation for Set-Associative Virtual Address Caches With Real Tags
May 1995 (vol. 44 no. 5)
pp. 719-723

Abstract—Stack simulation is a powerful cache analysis approach to generate the number of misses and write backs for various cache configurations in a single run. Unfortunately, none of the previous work on stack simulation has efficient stack algorithm for virtual address caches with real tags (V/R-type caches). In this paper, we devise an efficient stack simulation algorithm for analyzing V/R-type caches. Using markers with a valid range for synonym lines, our algorithm is able to keep track of stack distances for different cache configurations. In addition to cache miss ratios and write back ratios, our approach generates pseudonym frequency for all cache configurations under investigation.

[1] D. Clark, "Cache Performance in the VAX-11/780," ACM Trans. Computer Systems, vol. 1, no. 1, pp. 24-37, Feb. 1983.
[2] J. Gecsei,“Determining hit ratios in multilevel hierarchies,” IBM J. Research and Development, vol. 18, no. 4, pp. 316-327, July 1974.
[3] M. Hill,“Aspects of cache memory and instruction buffer performance,” PhD Thesis, Technical Report 87/381, Dept. of EECS, CS Div., Univ. of Calif., Berkeley, Nov. 1987.
[4] M. Hill and A. Smith, "Evaluating Associativity in CPU Caches," IEEE Trans. Computers, vol. 38, no. 12, pp. 1,612-1,630, Dec. 1989.
[5] IBM, IBM 3033 Processor Complex: Theory of Operation/Diagrams Manual. vol. 4, IBM Poughkeepsie, 1978.
[6] R. Lee, ``Precision Architecture,'' Computer, vol. 22, no. 1, pp. 78-91, Jan. 1989.
[7] R. Mattson,J. Gecsei,D. Slutz,, and I. Traiger,“Evaluation techniques for storage hierarchies,” IBM Systems J., vol. 9, no. 2, pp. 78-117, 1970.
[8] J. Heinrich,MIPS 4000 User's Manual, Prentice-Hall, 1993.
[9] T. Roirdan, et al. “System design using the MIPS R3000/3010 RISC chipset,” Digest of Papers Spring 1989 IEEE Compcon, pp. 494-498, 1989.
[10] J.G. Thompson and A.J. Smith, "Efficient (Stack) Algorithms for Analysis of Write-Back and Sector Memories," ACM Trans. Computer Systems, vol. 7, pp. 78-117, Feb. 1989.
[11] I. Traiger and D. Slutz,“One pass technique for the evaluation of memory hierarchies,” IBM Research Report, RJ 892 (#15563), July 1971.
[12] S.G. Tucker,“The IBM 3090 system: An overview,” IBM System J., vol. 25, no. 1, pp. 4-19, Jan. 1986.
[13] W.-H. Wang and J.-L. Baer, "Efficient Trace-Driven Simulation Methods for Cache Performance Analysis," ACM Trans. Computer Systems, Aug. 1991, pp. 222-241.
[14] C.E. Wu,Y. Hsu,, and Y.-H. Liu,"A Quantitative Evaluation of Cache Types for High-Performance Computer Systems," IEEE Trans. on Computers, Vol. 42, No. 10, Oct. 1993, pp. 1154-1162.

Index Terms:
Stack simulation, miss ratio, synonym, pseudonym, set-associative cache, V/R-type cache.
Yarsun Hsu, C. Eric Wu, Yew-Huey Liu, "Efficient Stack Simulation for Set-Associative Virtual Address Caches With Real Tags," IEEE Transactions on Computers, vol. 44, no. 5, pp. 719-723, May 1995, doi:10.1109/12.381961
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