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Delay-Insensitive Pipelined Communication on Parallel Buses
May 1995 (vol. 44 no. 5)
pp. 660-668

Abstract—Consider a communication channel that consists of several subchannels transmitting simultaneously and asynchronously. As an example of this scheme, we can consider a board with several chips. The subchannels represent wires connecting between the chips where differences in the lengths of the wires might result in asynchronous reception. In current technology, the receiver acknowledges reception of the message before the transmitter sends the following message. Namely, pipelined utilization of the channel is not possible.

Our main contribution is a scheme that enables transmission without an acknowledgment of the message, therefore enabling pipelined communication and providing a higher bandwidth. Moreover, our scheme allows for a certain number of transitions from a second message to arrive before reception of the current message has been completed, a condition that we call skew. We have derived necessary and sufficient conditions for codes that can tolerate a certain amount of skew among adjacent messages (therefore, allowing for continuous operation) and detect a larger amount of skew when the original skew is exceeded. These results generalize previously known results.

We have constructed codes that satisfy the necessary and sufficient conditions, studied their optimality, and devised efficient decoding algorithms. To the best of our knowledge, this is the first known scheme that permits efficient asynchronous communications without acknowledgment. Potential applications are in on-chip, on-board, and board to board communications, enabling much higher communication bandwidth.

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Index Terms:
Parallel communication, skew, pipelined channel, error-correcting codes, asynchronous communication.
Citation:
Jehoshua Bruck, Mario Blaum, "Delay-Insensitive Pipelined Communication on Parallel Buses," IEEE Transactions on Computers, vol. 44, no. 5, pp. 660-668, May 1995, doi:10.1109/12.381951
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