
This Article  
 
Share  
Bibliographic References  
Add to:  
Digg Furl Spurl Blink Simpy Del.icio.us Y!MyWeb  
Search  
 
ASCII Text  x  
Mao Xu, Xiaojun Shen, Xiangzu Wang, "An Optimal Algorithm for Permutation Admissibility to Multistage Interconnection Networks," IEEE Transactions on Computers, vol. 44, no. 4, pp. 604608, April, 1995.  
BibTex  x  
@article{ 10.1109/12.376176, author = {Mao Xu and Xiaojun Shen and Xiangzu Wang}, title = {An Optimal Algorithm for Permutation Admissibility to Multistage Interconnection Networks}, journal ={IEEE Transactions on Computers}, volume = {44}, number = {4}, issn = {00189340}, year = {1995}, pages = {604608}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.376176}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  An Optimal Algorithm for Permutation Admissibility to Multistage Interconnection Networks IS  4 SN  00189340 SP604 EP608 EPD  604608 A1  Mao Xu, A1  Xiaojun Shen, A1  Xiangzu Wang, PY  1995 KW  Adversary strategy KW  multistage interconnection network KW  permutation admissibility KW  transition matrix KW  window method. VL  44 JA  IEEE Transactions on Computers ER   
[1] C. Wu and T. Feng,“The universality of the shuffleexchange network,” IEEE Trans. Computers, vol. 30, pp. 324332, May 1981.
[2] D.P. Agrawal,“Graph theoretical analysis and design of multistageinterconnection networks,” IEEE Trans. Computers, vol. 32, pp. 637648, July 1983.
[3] C. Wu and T. Feng,“On a class of multistage interconnection networks,” IEEE Trans. Computers, vol. 29, pp. 694702, Aug. 1980.
[4] H.J. Siegel and R.J. McMillen,“The multistage cube: A versatile interconnection network,” Computer, pp. 6575, Dec. 1981.
[5] K. Padmanabhan and D.H. Lawrie,“A class of redundant path multistage interconnection networks,” IEEE Trans. Computers, vol. 32, pp. 10991108, Dec. 1983.
[6] K.Y. Lee,“On the rearrangeability of2(logN)−1stage permutation networks,” IEEE Trans. Computers, vol. 34, pp. 412425, May 1985.
[7] D.S. Parker,“Notes on shuffle/exchangetype switching networks,” IEEE Trans. Computers, vol. 29, pp. 213222, Mar. 1980.
[8] M.C. Pease,“The indirect binaryncube microprocessor array,” IEEE Trans. Computers, vol. 26, pp. 458473, May 1977.
[9] T.Y. Feng and W. Young,“AnO(log2N) control algorithm,” Int’l Conf. Parallel Processing, pp. 334340, 1985.
[10] C.J.A. Hsia and C.Y.R. Chen,“Permutation capability of multistage interconnection networks,” Int’l Conf. Parallel Processing, pp. I338I346, 1990.
[11] E.M. Reingold,J. Nievergelt,, and N. Deo,Combinatorial Algorithms: Theory and Practice, Prentice Hall, Englewood Cliffs, N.J., 1977.
[12] D.H. Lawrie,“Access and alignment of data in an array processor,” IEEE Trans. Computers, vol. 24, pp. 11451155, Dec. 1975.
[13] J.P. Hayes,Computer Architecture and Organization, Second Edition, McGrawHill, 1988.
[14] C.S. Raghavendra and A. Varma,“Faulttolerant multiprocessors with redundantpath interconnection networks,” IEEE Trans. Computers, vol. 35, No. 4, Apr. 1986.
[15] S. Baase,Computer Algorithms, Second Edition, Addison Wesley, 1989.