This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
A Fast VLSI-Efficient Self-Routing Permutation Network
March 1995 (vol. 44 no. 3)
pp. 448-453

Abstract—A multistage self-routing permutation network is presented. This network is constructed from concentrators and digit-controlled 2 \times 4 switches. A destination-tag routing scheme is used to realize any arbitrary permutation. The network has O(log^2\ N) gate-delay and uses O(N^2) VLSI-area, where N is the number of inputs. Assuming packet-switching is used for message transmission, the delay and VLSI-area of the network are smaller than those of any self-routing permutation network presented to date.

[1] D. Knuth, The Art of Computer Programming, vol. 3: Sorting and Searching. Addison-Wesley, 1973.
[2] K. Batcher,“Sorting networks and their applications,” AFIPS Spring Joint Computer Conf., vol. 32, pp. 307-314, 1968.
[3] T. Leighton, "Tight Bounds on the Complexity of Parallel Sorting," IEEE Trans. Computers, vol. 34, no. 4, pp. 344-354, Apr. 1985.
[4] F.T. Leighton,Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes.San Mateo, Calif.: Morgan Kaufmann, 1992.
[5] D.M. Koppelman and A.Y. Oruç, “A Self-Routing Permutation Network,” J. Parallel and Distributed Computing, vol. 10, no. 10, pp. 140-151, Oct. 1990.
[6] C. Jan and A.Y. Oruc,“Fast self-routing permutation networks,” Proc. 1991 Int’l Conf. Parallel Processing, pp. I-263-I-269.
[7] H.T. Szymanski,“A VLSI comparison of switch recursive banyan and crossbarinterconnection networks,” Proc. 1986 Int’l Conf. Parallel Processing, pp. 192-199.
[8] P. Mazumder,“Evaluation of three interconnection networks for CMOS VLSIimplementation,” Proc. 1986 Int’l Conf. on Parallel Processing, pp. 200-207.
[9] M.A. Franklin,D.F. Wann,, and W.J. Thomas,“Pin limitations and partitioning of VLSI interconnectionnetworks,” IEEE Trans. Computers, vol. 31, no. 11, pp. 1109-1116, Nov. 1982.
[10] M.A. Franklin,“VLSI performance comparison of banyan and crossbar communicationsnetworks,” IEEE Trans. Computers, vol. 30, no. 4, pp. 283-291, Apr. 1981.
[11] F.T. Leighton,M. Lepley,, and G.L. Miller,“Layouts for the shuffle-exchange graph based on the complex planediagram,” SIAM J. Alg. Disc. Meth., vol. 5, no. 2, pp. 202-215, June 1984.
[12] D.H. Lawrie,“Access and alignment of data in an array processor,” IEEE Trans. Computers, vol. 24, no. 12, pp. 1145-1155, Dec. 1975.
[13] M.C. Pease,“The indirect binary n-cube multiprocessor array,” IEEE Trans. Computers, vol. 26, no. 5, pp. 458-473, May 1977.
[14] T.H. Cormen and C.E. Leiserson,“A hyperconcentrator switch for routing bit-serial messages,” Proc. 1986 Int’l Conf. Parallel Processing, pp. 721-728.
[15] L.G. Valiant,“Graph-theoretic properties in computational complexity,” JCSS, vol. 13, no. 3, pp. 278-285, Dec. 1976.
[16] C.D. Thompson,“Generalized connection networks for parallel processorintercommunication,” IEEE Trans. Computers, vol. 27, no. 12, pp. 1119-1125, Dec. 1978.
[17] T.H. Cormen,“Efficient multichip partial concentrator switches,” Proc. 1987 Int’l Conf. Parallel Processing, pp. 525-532, 1987.
[18] T.H. Cormen,C.E. Leiserson, and R.L. Rivest,Introduction to Algorithms.Cambridge, Mass.: MIT Press/McGraw-Hill, 1990.

Index Terms:
Concentrator, permutation, network, radix-sorting, self-routing.
Citation:
Jose A.B. Fortes, Hasan Cam, "A Fast VLSI-Efficient Self-Routing Permutation Network," IEEE Transactions on Computers, vol. 44, no. 3, pp. 448-453, March 1995, doi:10.1109/12.372036
Usage of this product signifies your acceptance of the Terms of Use.