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A Fast VLSI-Efficient Self-Routing Permutation Network
March 1995 (vol. 44 no. 3)
pp. 448-453

Abstract—A multistage self-routing permutation network is presented. This network is constructed from concentrators and digit-controlled 2 \times 4 switches. A destination-tag routing scheme is used to realize any arbitrary permutation. The network has O(log^2\ N) gate-delay and uses O(N^2) VLSI-area, where N is the number of inputs. Assuming packet-switching is used for message transmission, the delay and VLSI-area of the network are smaller than those of any self-routing permutation network presented to date.

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Index Terms:
Concentrator, permutation, network, radix-sorting, self-routing.
Jose A.B. Fortes, Hasan Cam, "A Fast VLSI-Efficient Self-Routing Permutation Network," IEEE Transactions on Computers, vol. 44, no. 3, pp. 448-453, March 1995, doi:10.1109/12.372036
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