This Article 
 Bibliographic References 
 Add to: 
Test Generation for Path Delay Faults Using Binary Decision Diagrams
March 1995 (vol. 44 no. 3)
pp. 434-447

Abstract—A new test generation technique for path delay faults in circuits employing scan/hold type flip-flops is presented. Reduced ordered binary decision diagrams (ROBDDs) are used to represent Boolean functions realized by all signals in the circuit, as well as to represent the constraints to be satisfied by the delay fault test. Two faults are considered for each path in the circuit. For each fault, a pair of constraint functions, corresponding to the two time frames that constitute a transition, is evaluated. If the constraint function in the second time frame is non-null, robust - hazard-free - test generation for the delay fault is attempted. A robust test thus generated belongs either to the class of fully transitional path (FTP) tests or to the class of single input transition (SIT) tests. If a robust test cannot be found, the existence of a non-robust test is checked. Boolean algebraic manipulation of the constraint functions guarantees that if neither robust nor non-robust tests exist, the fault is undetectable. In its present form the method is applicable to all circuits that are amenable to analysis using ROBDDs. An implementation of this technique is used to analyze delay fault testability of ISCAS ’89 benchmark circuits. These results show that the algebraic technique is one to two orders of magnitude faster than previously reported methods based on branch-and-bound algorithms.

[1] M. Abramovici,M.A. Breuer,, and A.D. Friedman,Digital Systems Testing and Testable Design, Computer Science Press, W.H. Freeman, N.Y., 1990.
[2] P. Agrawal,V.D. Agrawal,, and S.C. Seth,“A new method for generating tests for delay faults in non-scan circuits,” Proc. Fifth Int’l Conf. on VLSI Design,Bangalore, India, Jan. 1992, pp. 4-11.
[3] S.B. Akers,“Binary decision diagrams,” IEEE Trans on Computers, vol. 27, pp. 509-164, June 1978.
[4] D. Bhattacharya,P. Agrawal,, and V.D. Agrawal,“Delay fault test generation for scan/hold circuits using Boolean expressions,” Proc. 29th Design Automation Conf., June 1992, pp. 159-164.
[5] D. Bhattacharya and P. Agrawal,“Boolean algebraic test generation using a distributed system,” Proc. Int’l Conf. on Computer-Aided Design, Nov. 1993, pp. 440-444.
[6] S. Bose, P. Agrawal, and V.D. Agrawal, "Logic Systems for Path Delay Test Generation," Proc. EURO-DAC, pp. 200-205, Sept. 1993.
[7] K.S. Brace, R.L. Rudell, and R.E. Bryant, Efficient Implementation of a BDD Package Proc. Design Automation Conf., pp. 40-45, 1990.
[8] F. Brglez, D. Bryan, and K. Kozminski, "Combinatorial Profiles of Sequential Benchmark Circuits," Proc. IEEE Int'l. Symp. Circuits and Systems, IEEE Computer Soc. Press, Los Alamitos, Calif., 1989, pp. 1929-1934.
[9] R.E. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation," IEEE Trans. Computers, Vol. C-35, No. 8, Aug. 1986, pp. 667-690.
[10] T.J. Chakraborty, V.D. Agrawal, and M.L. Bushnell, "Delay Fault Models and Test Generation for Random Logic Sequential Circuits," Proc. 29th Design Automation Conf., pp. 165-172, June 1992.
[11] S.T. Chakradar,M.A. Iyer, and V.D. Agrawal,"Energy minimization based delay testing," Proc. European Design Automation Conf., pp. 280-284, 1992.
[12] K.T. Cheng,S. Devada,, and K. Kuetzer,“Delay fault test generation and synthesis for testability under a standard scan design methodology,” IEEE Trans. on Computer Aided Design, vol. 12, pp. 1217-1231, Aug. 1993.
[13] S. Dasgupta,R.G. Walther,T.W. Williams,, and E.B. Eichelberger,“An enhancement to LSSD and some applicationsof LSSD in reliabilty, availability, and survivability,” Proc. 11th Fault-Tolerant Computer Symp., June 1981, pp. 32-34.
[14] K. Fuchs, F. Fink, and M.H. Schulz, "DYNAMITE: An Efficient Automatic Test Pattern Generation System for Path Delay Faults," IEEE Trans. Computer-Aided Design, vol. 10, pp. 1,323-1,335, Oct. 1991.
[15] A. Ghosh, S. Devadas, and A.R. Newton, "Test Generation and Verification for Highly Sequential Circuits," IEEE Trans. Computer-Aided Design, pp. 652-667, May 1991.
[16] C.T. Glover and M.R. Mercer,“A method of delay fault test generation,” Proc. 25th ACM/IEEE Design Automation Conf., June 1988, pp. 90-95.
[17] P. Goel,“An implicit enumeration algorithm to generate tests for combinational logic,” IEEE Trans. on Computers, vol. 30, pp. 215-222, Mar. 1981.
[18] C.Y. Lee,“Representation of switching circuits by binary-decision programs,” Bell Systems Tech. J., vol. 38, pp. 985-999, July 1959.
[19] J.P. Lesser and J.J. Shedletsky,“An experimental delay test generator for LSI logic,” IEEE Trans. on Computers, vol. 29, pp. 235-248, Mar. 1980.
[20] C.J. Lin and S. Reddy,“On delay fault testing in logic circuits,” IEEE Trans. on Computer Aided Design, vol. 6, no. 5, pp. 694-703, Sept. 1987.
[21] P.C. McGeer,A. Saldanha,P.R. Stephan,R.K. Brayton,, and A.L. Sangiovanni-Vincentelli,“Timing analysis and delay-fault test generation using path-recursive functions,” Proc. Int’l Conf. on Computer-Aided Design, Nov. 1991, pp. 180-183.
[22] Y.K. Malaiya and R. Narayanaswamy,“Modeling and testing for timing faults in synchronous sequential circuits,” IEEE Design&Test of Computers, vol. 1, pp. 62-74, Nov. 1984.
[23] A.K. Pramanick and S.M. Reddy,“On the fault coverage of delay fault detecting tests,” Proc. First European Design Automation Conf., Mar. 1990, pp. 334-338.
[24] A.K. Pramanick and S.M. Reddy, "On Multiple Path Propagating Tests for Path Delay Faults," Proc. IEEE Int'l Test Conf., pp. 393-402, 1991.
[25] A.K. Pramanick and S.M. Reddy,“On unified delay fault testing,” Proc. Sixth Int’l Conf. on VLSI Design, Jan. 1993, pp. 265-268.
[26] A. Saldhana, R.K. Brayton, and A.L. Sangiovanni-Vincentelli, "Equivalence of Robust Delay-Fault and Single Stuck-Fault Test Generation," Proc. IEEE/ACM Design Automation Conf., pp. 173-176, 1992.
[27] G.L. Smith,“Model for delay faults based upon paths,” Proc. Int’l Test Conf., Nov. 1985, pp. 342-349.
[28] T. Stanion and D. Bhattacharya,“TSUNAMI: A path-oriented scheme for algebraic test generation,” Proc. 21st Symp. on Fault-Tolerant Computers, June 1991, pp. 36-43.

Index Terms:
Boolean algebraic test generation, binary decision diagrams, delay faults, redundant delay faults, robust delay tests, scan testing of delay faults.
Prathima Agrawal, Debashis Bhattacharya, Vishwani D. Agrawal, "Test Generation for Path Delay Faults Using Binary Decision Diagrams," IEEE Transactions on Computers, vol. 44, no. 3, pp. 434-447, March 1995, doi:10.1109/12.372035
Usage of this product signifies your acceptance of the Terms of Use.