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Fault Detection in Multiprocessor Systems and Array Processors
March 1995 (vol. 44 no. 3)
pp. 383-393

Abstract—Off-line testing of large multiprocessor networks or VLSI chips with many outputs requires a large volume of memory for reference data storage. Space compaction combined with time compression of test responses can essentially reduce an overhead required for testing and diagnosis. In this paper, we discuss the problem of optimal design for space compressors (compactors), to minimize the number of observation points for detection of single faulty components in multiprocessor networks. A space compactor is assumed to be followed by a time compressor, to detect a fault not necessarily manifesting itself for a single test pattern.

We formulate the rules of design for a space compaction matrix for the topology of the circuit-under-test (CUT) modeled by an arbitrary acyclic graph. Tree arrays and Fourier transform networks are considered as examples. The lower and upper bounds on the number of space compactor outputs are obtained, and optimal space compaction matrices are determined for above mentioned CUT topologies. Simple procedures for design of off-line testing devices with built-in self-testing are presented. Estimations on a complexity of proposed designs are given.

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Index Terms:
Fourier transform networks, fault detection in VLSI devices, data compression (compaction), integrated circuits testing, off-line testing; VLSI devices testing.
Citation:
Tatyana D. Roziner, Mark G. Karpovsky, Claudio Moraga, "Fault Detection in Multiprocessor Systems and Array Processors," IEEE Transactions on Computers, vol. 44, no. 3, pp. 383-393, March 1995, doi:10.1109/12.372031
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