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IEEE Transactions on Computers
March 1995 (vol. 44 no. 3)
ISSN: 0018-9340
Table of Contents
Papers
The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors
(Abstract)
Daniel M. Lavery
Pohua P. Chang
Scott A. Mahlke
William Y. Chen
Wen-mei W. Hwu
pp. 353-370
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CA-Based Byte Error-Correcting Code
(Abstract)
Indranil Sen Gupta
Dipanwita Roy Chowdhury
Parimal Pal Chaudhuri
pp. 371-382
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Fault Detection in Multiprocessor Systems and Array Processors
(Abstract)
Tatyana D. Roziner
Mark G. Karpovsky
Claudio Moraga
pp. 383-393
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Management of Partially Safe Buffers
(Abstract)
Kenneth Salem
Sedat Akyürek
pp. 394-407
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A Fault Tolerant Hybrid Memory Structure and Memory Management Algorithms
(Abstract)
Dhiraj K. Pradhan
Nicholas S. Bowen
pp. 408-418
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Analytic Modeling and Comparisons of Striping Strategies for Replicated Disk Arrays
(Abstract)
Philip S. Yu
Arif Merchant
pp. 419-433
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Test Generation for Path Delay Faults Using Binary Decision Diagrams
(Abstract)
Prathima Agrawal
Debashis Bhattacharya
Vishwani D. Agrawal
pp. 434-447
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Brief Contributions
A Fast VLSI-Efficient Self-Routing Permutation Network
(Abstract)
Jose A.B. Fortes
Hasan Cam
pp. 448-453
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Fast Evaluation of the Elementary Functions in Single Precision
(Abstract)
E. Goto
W.f. Wong
pp. 453-457
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Practical Delay Enforced Multistream (DEMUS) Control of Deeply Pipelined Processors
(Abstract)
pp. 458-462
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Computing Reliability Intervals for k-Resilient Protocols
(Abstract)
Yennun Huang
Sampath Rangarajan
Satish K. Tripathi
pp. 462-466
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Algorithms for Scheduling Imprecise Computations with Timing Constraints to Minimize Maximum Error
(Abstract)
Jane W.S. Liu
Wei-Kuan Shih
pp. 466-471
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Parametric Dispatching of Hard Real-Time Tasks
(Abstract)
William Pugh
Richard Gerber
Manas Saksena
pp. 471-479
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