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On Fault Simulation for Synchronous Sequential Circuits
February 1995 (vol. 44 no. 2)
pp. 335-340

Abstract—We investigate the considerations to be employed in designing a fault simulator for synchronous sequential circuits described at the gate-level. Three testing strategies and three methods of handling unknown state variable values are considered. Every combination of a test strategy and a method of handling unknown state variable values defines a different fault simulation procedure. Experimental results are presented to demonstrate the different fault coverage levels achievable by the various procedures. Based on these results, a fault simulation procedure that combines the various considerations is proposed.

Index Terms—Fault simulation, Multiple observation time test strategy, Single observation time test strategy, Synchronous sequential circuits, Three-value logic.

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Citation:
Irith Pomeranz, Sudhakar M. Reddy, "On Fault Simulation for Synchronous Sequential Circuits," IEEE Transactions on Computers, vol. 44, no. 2, pp. 335-340, Feb. 1995, doi:10.1109/12.364543
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