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On Fault Simulation for Synchronous Sequential Circuits
February 1995 (vol. 44 no. 2)
pp. 335-340
ASCII Text
x 
 
Irith Pomeranz, Sudhakar M. Reddy, "On Fault Simulation for Synchronous Sequential Circuits," IEEE Transactions on Computers, vol. 44, no. 2, pp. 335-340, February, 1995.
 
 
BibTex
x
 
@article{ 10.1109/12.364543,
author = {Irith Pomeranz and Sudhakar M. Reddy},
title = {On Fault Simulation for Synchronous Sequential Circuits},
journal ={IEEE Transactions on Computers},
volume = {44},
number = {2},
issn = {0018-9340},
year = {1995},
pages = {335-340},
doi = {http://doi.ieeecomputersociety.org/10.1109/12.364543},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - On Fault Simulation for Synchronous Sequential Circuits
IS - 2
SN - 0018-9340
SP335
EP340
EPD - 335-340
A1 - Irith Pomeranz,
A1 - Sudhakar M. Reddy,
PY - 1995
VL - 44
JA - IEEE Transactions on Computers
ER -
 

Abstract—We investigate the considerations to be employed in designing a fault simulator for synchronous sequential circuits described at the gate-level. Three testing strategies and three methods of handling unknown state variable values are considered. Every combination of a test strategy and a method of handling unknown state variable values defines a different fault simulation procedure. Experimental results are presented to demonstrate the different fault coverage levels achievable by the various procedures. Based on these results, a fault simulation procedure that combines the various considerations is proposed.

Index Terms—Fault simulation, Multiple observation time test strategy, Single observation time test strategy, Synchronous sequential circuits, Three-value logic.

[1] H. Fujiwara, Logic Testing and Design for Testability. MIT Press, 1985.
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[4] I. Pomeranz and S. M. Reddy,“Test generation for synchronous sequential circuits using multiple observation times,”inProc. 21st Fault-Tolerant Computing Symp., June 1991, pp. 52–59; also in I. Pomeranz and S. M. Reddy,“The multiple observation time test strategy,”IEEE Trans. Comput., pp. 627–637, May 1992.
[5] J. P. Roth,“Diagnosis of automata failures: A calculus and a method,”IBM J. Res. Develop.,vol. 10, pp. 278–291, July 1966.
[6] I. Pomeranz and S. M. Reddy,“Classification of faults in synchronous sequential circuits,”IEEE Trans. Comput., pp. 1066–1077, Sept. 1993.
[7] I. Pomeranz, S. M. Reddy, and L. N. Reddy,“Increasing fault coverage for synchronous sequential circuits by the multiple observation time test strategy,”inProc. 1991 Int. Conf. Comput.-Aided Design, Nov. 1991, pp. 454–457.
[8] I. Pomeranz and S. M. Reddy,“Applications of homing sequences for synchronous sequential circuits,”inProc. 2nd Asia Test Symp., Nov. 1993, pp. 324–329.
[9] H. Cho, S.-W. Jeong, F. Somenzi, and C. Pixley,“Synchronizing sequences and symbolic traversal techniques in test generation,”J. Electron. Testing: Theory and Appl.,vol. 4, pp. 19–31, Feb. 1993.

Citation:
Irith Pomeranz, Sudhakar M. Reddy, "On Fault Simulation for Synchronous Sequential Circuits," IEEE Transactions on Computers, vol. 44, no. 2, pp. 335-340, Feb. 1995, doi:10.1109/12.364543
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