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Fault Coverage and Test Length Estimation for Random Pattern Testing
February 1995 (vol. 44 no. 2)
pp. 234-247

Abstract— Fault coverage and test length estimation in circuits under random test is the subject of this paper. Testing by a sequence of random input patterns is viewed as sequential sampling of faults from a given fault universe. Based on this model, the probability mass function (\mbi{pmf}) of fault coverage and expressions for all its moments are derived. This provides a means for computing estimates of fault coverage as well as determining the accuracy of the estimates.

Test length, viewed as waiting time on fault coverage, is analyzed next. We derive expressions for its \mbi{pmf} and its probability generating function (\mbi{pgf}). This allows computation of all the higher order moments. In particular, expressions for mean and variance of test length for any specified fault coverage are derived. This is a considerable enhancement of the state of the art in techniques for predicting test length as a function of fault coverage. It is shown that any moment of test length requires knowledge of all the moments of fault coverage, and hence, its \mbi{pmf}. For this reason, expressions for approximating its expected value and variance, for user specified error bounds, are also given. A methodology based on these results is outlined. Experiments carried out on several circuits demonstrate that this technique is capable of providing excellent predictions of test length. Furthermore it is shown, as with fault coverage prediction, that estimates of variances can be used to bound average test length quite effectively.

Index Terms—Fault coverage, test length, urn models, occupancy, waiting time.

[1] M. Abramovici, M. A. Breuer, and A. D. Friedman,Digital Systems Testing and Testable Design. Rockville, MD: Computer Science Press, 1990.
[2] V. D. Agrawal,“Sampling techniques for determining fault coverage in LSI circuits,”J. Digital Syst., vol. V, no. 3, pp. 189–202.
[3] M. A. Breuer and A. A. Ismaeel,“Roving emulation as a fault detection mechanism,”IEEE Trans. Comput., vol. C-35, pp. 933–939, Nov. 1986.
[4] F. N. David and D. E. Barton,Combinatorial Chance. London, U.K.: Charles Griffin&Company Limited, 1962.
[5] R. David, M. Fuentes, and B. Courtois,“Random pattern testing versus deterministic testing of RAM's,”IEEE Trans. Comput., vol. 38, pp. 637–650, May 1989.
[6] P. Goel,“Test generation costs analysis and projections,”inProc. 17th Design Automat. Conf., 1980, pp. 77–84.
[7] R. L. Graham, D. E. Knuth, and O. Patashnik,Concrete Mathematics. Reading, MA: Addison-Wesley, 1989.
[8] W. K. Huang, M. Lightner, and F. Lombardi,“Predicting fault coverage for random testing of combinational circuits,”inProc. IEEE Int. Test Conf., 1987, pp. 843–848.
[9] S. K. Jain and V. D. Agrawal,“STAFAN: An alternative to fault simulation,”inProc. 21st Design Automat. Conf., 1984, pp. 18–23.
[10] S. Jayaraman,“Test generation for single stuck-at faults in combinational circuits using binary decision diagrams,”Masters Thesis, Dept. of Electrical Engineering, Southern Illinois University–Carbondale, 1993.
[11] K. Kim, D. S. Ha, and J. G. Tront,“On using signature registers as pseudorandom pattern generators in built-in self-testing,”IEEE Trans. Computer-Aided Design, vol. 7, pp. 919–928, Aug. 1988.
[12] D.E. Knuth, The Art of Computer Programming, vol. 1,Addison Wesley, second ed. 1973.
[13] R. Krieger,“PLATO: A tool for computing exact signal probabilities,”inProc. 6th Int. Conf. VLSI Design, Bombay, 1993, pp. 65–68.
[14] A. Majumdar and S. B. K. Vrudhula,“Random-test length estimation: Analysis and techniques,”Tech. Rep. SIUC/DEE/TR-93-2, Dept. of Electrical Engineering, Southern Illinois University at Carbondale, 1993.
[15] A. Majumdar,“WRAPTURE: A tool for evaluation and optimization of weights for weighted random pattern testing,”inProc. ICCD, 1994, pp. 288–291.
[16] Y. K. Malaiya and S. Yang,“The coverage problem for random testing,”inProc. Int. Test Conf., 1984, pp. 237–242.
[17] S. Sastry and A. Majumdar,“A branching process model for observability analysis of combinational circuits,”inProc. 28th Design Automat. Conf., 1991, pp. 452–457.
[18] J. Savir and P. H. Bardell,“On random pattern test length,”IEEE Trans. Comput., vol. C-33, pp. 467–474, June 1984.
[19] S. C. Seth, V. D. Agrawal, and H. Farhat,“A statistical theory of digital circuit testability,”IEEE Trans. Comput., vol. 39, pp. 582–586, Apr. 1990.
[20] K. D. Wagner, C. K. Chin, and E. J. McCluskey,“Pseudorandom testing,”IEEE Trans. Comput., vol. C-36, pp. 332–343, Mar. 1987.

Amitava Majumdar, Sarma B. K. Vrudhula, "Fault Coverage and Test Length Estimation for Random Pattern Testing," IEEE Transactions on Computers, vol. 44, no. 2, pp. 234-247, Feb. 1995, doi:10.1109/12.364535
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