Publication 1995 Issue No. 2 - February Abstract - Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers
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Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers
February 1995 (vol. 44 no. 2)
pp. 223-233
 ASCII Text x Sybille Hellebrand, Janusz Rajski, Steffen Tarnick, Srikanth Venkataraman, Bernard Courtois, "Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers," IEEE Transactions on Computers, vol. 44, no. 2, pp. 223-233, February, 1995.
 BibTex x @article{ 10.1109/12.364534,author = {Sybille Hellebrand and Janusz Rajski and Steffen Tarnick and Srikanth Venkataraman and Bernard Courtois},title = {Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers},journal ={IEEE Transactions on Computers},volume = {44},number = {2},issn = {0018-9340},year = {1995},pages = {223-233},doi = {http://doi.ieeecomputersociety.org/10.1109/12.364534},publisher = {IEEE Computer Society},address = {Los Alamitos, CA, USA},}
 RefWorks Procite/RefMan/Endnote x TY - JOURJO - IEEE Transactions on ComputersTI - Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift RegistersIS - 2SN - 0018-9340SP223EP233EPD - 223-233A1 - Sybille Hellebrand, A1 - Janusz Rajski, A1 - Steffen Tarnick, A1 - Srikanth Venkataraman, A1 - Bernard Courtois, PY - 1995VL - 44JA - IEEE Transactions on ComputersER -

Abstract—In this paper, we propose a new scheme for Built-In Test (BIT) that uses Multiple-polynomial Linear Feedback Shift Registers (MP-LFSR's). The same MP-LFSR that generates random patterns to cover easy to test faults is loaded with seeds to generate deterministic vectors for difficult to test faults. The seeds are obtained by solving systems of linear equations involving the seed variables for the positions where the test cubes have specified values. We demonstrate that MP-LFSR's produce sequences with significantly reduced probability of linear dependence compared to single polynomial LFSR's. We present a general method to determine the probability of encoding as a function of the number of specified bits in the test cube, the length of the LFSR and the number of polynomials. Theoretical analysis and experiments show that the probability of encoding a test cube with $s$ specified bits in an $s$-stage LFSR with 16 polynomials is 1–10$^\left\{-6\right\}.$ We then present the new BIT scheme that allows for an efficient encoding of the entire test set. Here the seeds are grouped according to the polynomial they use and an implicit polynomial identification reduces the number of extra bits per seed to one bit. The paper also shows methods of processing the entire test set consisting of test cubes with varied number of specified bits. Experimental results show the tradeoffs between test data storage and test application time while maintaining complete fault coverage.

Index Terms—Built-In Test, hardware test pattern generators, input test data compression and decompression, multiple-polynomial LFSR, reseeding, scan design.

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Citation:
Sybille Hellebrand, Janusz Rajski, Steffen Tarnick, Srikanth Venkataraman, Bernard Courtois, "Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers," IEEE Transactions on Computers, vol. 44, no. 2, pp. 223-233, Feb. 1995, doi:10.1109/12.364534