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Synthesis of Delay-Verifiable Combinational Circuits
February 1995 (vol. 44 no. 2)
pp. 213-222

Abstract—We address the problem of testing circuits for temporal correctness. A circuit is considered delay-verifiable if its timing correctness can be established by applying delay tests. It is shown that verifying the timing of a circuit may require tests which can detect the simultaneous presence of more than one path delay fault. We provide a general framework for examining delay-verifiability by introducing a special class of faults called primitive path delay faults. It is necessary and sufficient to test every fault in this class to ensure the temporal correctness of combinational circuits. Based on this result, we develop a synthesis procedure for combinational circuits that can be tested for correct timing. Experimental data show that such implementations usually require less area than completely delay testable implementations.

Index Terms—Testing for timing correctness, path-delay faults, delay-verification tests, primitive path-delay faults, synthesis for delay-verifiability.

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Citation:
Wuudiann Ke, Premachandran R. Menon, "Synthesis of Delay-Verifiable Combinational Circuits," IEEE Transactions on Computers, vol. 44, no. 2, pp. 213-222, Feb. 1995, doi:10.1109/12.364533
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