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Issue No.02 - February (1995 vol.44)
pp: 170-180
ABSTRACT
<p><it>Abstract—</it>This paper describes fault-tolerant and error detection features in HaL's <it>memory management unit</it> (MMU). The proposed fault-tolerant features allow recovery from transient errors in the MMU. It is shown that these features were natural choices considering the architectural and implementation constraints in the MMU's design environment. Three concurrent error detection and correction methods employed in address translation and coherence tables in the MMU are described. Virtually-indexed and virtually-tagged cache architecture is exploited to provide an almost fault-secure hardware coherence mechanism in the MMU, with very small performance overhead (less than 0.01% in the instruction throughput). Low overhead linear polynomial codes have been chosen in these designs to minimize both the hardware and software instrumentation impact.</p><p><it>Index Terms—</it>Coherence, concurrent error detection/ correction, linear polynomial codes, translation lookaside buffers, content addressable memory, memory management unit, fault-tolerant computing.</p>
CITATION
Nirmal R. Saxena, Chih-Wei David Chang, Kevin Dawallu, Jaspal Kohli, Patrick Helland, "Fault-Tolerant Features in the HaL Memory Management Unit", IEEE Transactions on Computers, vol.44, no. 2, pp. 170-180, February 1995, doi:10.1109/12.364529
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