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  • 1995
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  • Abstract - A Remark on 'Reducing Iteration Time when Result Digit is Zero for Radix-2 SRT Division and Square Root with Redundant Remainders'
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A Remark on 'Reducing Iteration Time when Result Digit is Zero for Radix-2 SRT Division and Square Root with Redundant Remainders'
January 1995 (vol. 44 no. 1)
pp. 144-146

Abstract—In a previous paper by P. Montuschi and L. Ciminiera, an architecture for shared radix 2 division and square root, has been presented whose main characteristic is the ability to avoid any addition/subtraction, when the digit 0 has been selected. Here, we emphasize the characteristics of the digit selection mechanism used by Montuschi and Ciminiera by presenting a small modification of the digit selection hardware, which has the benefit to further reduce the computation delay with respect to the time estimated in that work.

[1] European Silicon Structures, ES2 ECPD10 Library Databook, Apr. 1991.
[2] M. D. Ercegovac and T. Lang,“On-the-fly rounding for division and square root,”inProc. 9th IEEE Symp. Comput. Arithmetic, Santa Monica, CA, Sept. 1989, pp. 169–173.
[3] M.D. Ercegovac and T. Lang, Division and Square Root—Digit-Recurrence Algorithms and Implementations. Kluwer Academic, 1994.
[4] P. Montuschi and L. Ciminiera,“Reducing iteration time when result digit is zero for Radix-2 SRT division and square root with redundant remainders,”IEEE Trans. Comput., vol. 42, no. 2, pp. 239–246, Feb. 1993.

Citation:
Paolo Montuschi, Luigi Ciminiera, "A Remark on 'Reducing Iteration Time when Result Digit is Zero for Radix-2 SRT Division and Square Root with Redundant Remainders'," IEEE Transactions on Computers, vol. 44, no. 1, pp. 144-146, Jan. 1995, doi:10.1109/12.368000
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