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The Connection Network Class for Fault Tolerant Meshes
January 1995 (vol. 44 no. 1)
pp. 131-138

Abstract—The Connection Network is a new class of Fault Tolerant Mesh networks which uses a switched bus net in a mesh-connected array. Much use of Rail Networks for Fault Tolerance of WSI is reported in the literature. The Connection Network simplifies the Rail Networks, and is superior in terms of theoretical power to survive faults.

We demonstrate this by general comparison of the Connection and Rail Classes of networks, and a specific comparison between the Single Connection, Double Rail and Symmetric Networks.

Our results show that the Connection Network is more powerful in terms of statistical theoretical constants and flexibility of algorithms; comparable in terms of VLSI area usage; has less signal delay on interconnections between Processing Elements; facilitates the implementation of switches which are fault tolerant and gracefully degradable; and allows the addition of redundant rails to cope with wire failure.

[1] B. Beresford-Smith and H. Schröder,“Effective reconfiguration in fault tolerant mesh-connected networks,”Australian Comput. J., vol. 21, no. 2, pp. 79–84, May 1989
[2] M. Chean and J. A. B. Fortes,“Full-use-of-suitable-spares (FUSS) approach to hardware reconfiguration for fault-tolerant processor arrays,”IEEE Trans. Comput., vol. 39, no. 4, Apr. 1990.
[3] V. N. Doniants, V. G. Lazarev, M. G. Sami, and R. Stefanelli,“Reconfiguration of VLSI arrays: A technique for increased flexibility and reliability,”Microprocessing and Microprogramming, vol. 16, no. 2–3, pp. 101–106, Sept.–Oct. 1985.
[4] G. E. Farr and H. Schröder,“An evaluation of reconfiguration algorithms in fault tolerant processor arrays,”inAdvanced Res. in VLSI. Proc. Fifth MIT Conf., MIT Press, Mar. 1988, pp. 131–148.
[5] J. S. N. Jean, H. C. Fu, and S. Y. Kung,“Yield enhancement for WSI array processors using two-and-half-track switches,”inProc. Int. Conf. Wafer Scale Integrat., IEEE, 1990, pp. 243–251.
[6] K. S. Hedlund and L. Snyder,“Wafer-scale integration of the configurable highly parallel (CHiP) processor,”inProc. Int. Conf. Parallel Processing, IEEE, 1982, pp. 262–264.
[7] S. Y. Kung, C. W. Chang, and C. W. Jen,“Real-time reconfiguration for fault-tolerant VLSI array processors,”inProc. Real-Time Syst. Symp., IEEE Computer Soc, IEEE, Dec. 2–4, 1986, pp. 46–54.
[8] T. Leighton and C. E. Leiserson,“Wafer-scale integration of systolic arrays,”IEEE Trans. Comput., vol. C-34 , no. 5, pp. 448–461, May 1985.
[9] F. Lombardi, M. G. Sami, and R. Stefanelli,“Reconfiguration of VLSI arrays by covering,”IEEE Trans. Comput.-Aided Design of Integrat. Circ. Syst., vol. 8, no. 9, pp. 952–965, Sept. 1989.
[10] F. Lombardi and D. Sciuto,“Reconfiguration in WSI arrays using minimum spanning trees,”in1987 Proc. Fourth Int. IEEE VLSI Multilevel Interconnection Conf., IEEE, pp. 547–550, June 1987.
[11] R. Mazzaferri and T. McDonald (Murray),“Bounds on minimum atomic fail pattern sizes for selected networks,”Rep. no. EE9323, Dep. of Elec. Comput. Eng., Univ. of Newcastle, Newcastle NSW 2308 Australia, July, 1993.
[12] R. Mazzaferri and H. Schröder,“A superior class of networks for reconfigurable meshes,”inProc. 6th Int. Parallel Processing Symp., IEEE Computer Society, IEEE, Mar. 23–26, 1992, pp. 437–442.
[13] T. McDonald (Murray) and Heiko Schröder,“C$_3$—A powerful connection network for fault tolerance,”inProc. Pacific Rim Int. Symp. Fault Tolerant Syst., IEEE Computer Society Press, Sept. 1991, pp. 102–107.
[14] ——,“A new simple and powerful mesh network for reconfigurable arrays,”The Australian Comput. Sci. Commun., vol. 14, no. 1, pp. 589–601, Jan. 1992.
[15] R. Negrini, M. Sami, and R. Stefanelli,Fault-Tolerance Through Reconfiguration of VLSI and WSI Arrays. Cambridge, MA: MIT Press, 1989.
[16] M. Sami and R. Stefanelli,“Fault-tolerance and functional reconfiguration in VLSI arrays,”inProc. IEEE Int. Symp. Circ. Syst., 1986, pp. 643–648.
[17] ——,“Fault tolerant computing approaches,”inSystolic Signal Processing Systems. New York: Marcel Dekker, 1987, ch. 8, pp. 327–388.

Citation:
Richard Mazzaferri, Teresa M. Murray, "The Connection Network Class for Fault Tolerant Meshes," IEEE Transactions on Computers, vol. 44, no. 1, pp. 131-138, Jan. 1995, doi:10.1109/12.368002
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