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A Design of Reed-Solomon Decoder with Systolic-Array Structure
January 1995 (vol. 44 no. 1)
pp. 118-122

Abstract—This brief contribution proposes a new class of systolic-arrays to perform Binary Reed–Solomon (RS) decoding procedures including erasure correction. Such RS decoder is suitable for VLSI implementation since the arrays consist of simple processing elements of the same type.

Index—Error and erasure correction, high-speed processing, Reed–Solomon decoder, systolic-array, VLSI implementation

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Citation:
Keiichi Iwamura, Yasunori Dohi, Hideki Imai, "A Design of Reed-Solomon Decoder with Systolic-Array Structure," IEEE Transactions on Computers, vol. 44, no. 1, pp. 118-122, Jan. 1995, doi:10.1109/12.368005
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