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Routing in a Three-Dimensional Chip
January 1995 (vol. 44 no. 1)
pp. 106-117

As the very large scale integration (VLSI) technology approaches its fundamental scaling limit at about 0.2 \mum, it is reasonable to consider three-dimensional (3-D) integration to enhance packing density and speed performance. With additional functional units packed into one chip in a 3-D space, computer-aided design (CAD) tools are demanded to ease the complicated design work. This paper presents a 100% completion achievable routing methodology. The routing methodology is based on the two-dimensional (2-D) channel routing methodology; thus, it is called a 3-D channel routing methodology. With the routing methodology, a 3-D routing problem is decomposed into two 2-D routing subproblems: intra-layer routing that interconnects terminals on the same layer, which can be done by using a 2-D channel router, and inter-layer routing that interconnects terminals on different layers. The inter-layer routing problem is transformed into a 2-D channel routing problem and the transformation is made in some 3-D channels. Detailed discussions are given for the 3-D to 2-D transformation. Optimization of the transformation is shown to be NP-complete. Thus, simulated annealing is used to optimize the transformation.

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Index Terms:
Silicon-on-insulator, three-dimensional chip, three-dimensional routing, channel routing, inter-layer routing, intra layer routing, NP-routing, constraint graph, computed-aided design.
Chao Chi Tong, Chuan-lin Wu, "Routing in a Three-Dimensional Chip," IEEE Transactions on Computers, vol. 44, no. 1, pp. 106-117, Jan. 1995, doi:10.1109/12.368006
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