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Routing in a Three-Dimensional Chip
January 1995 (vol. 44 no. 1)
pp. 106-117

As the very large scale integration (VLSI) technology approaches its fundamental scaling limit at about 0.2 \mum, it is reasonable to consider three-dimensional (3-D) integration to enhance packing density and speed performance. With additional functional units packed into one chip in a 3-D space, computer-aided design (CAD) tools are demanded to ease the complicated design work. This paper presents a 100% completion achievable routing methodology. The routing methodology is based on the two-dimensional (2-D) channel routing methodology; thus, it is called a 3-D channel routing methodology. With the routing methodology, a 3-D routing problem is decomposed into two 2-D routing subproblems: intra-layer routing that interconnects terminals on the same layer, which can be done by using a 2-D channel router, and inter-layer routing that interconnects terminals on different layers. The inter-layer routing problem is transformed into a 2-D channel routing problem and the transformation is made in some 3-D channels. Detailed discussions are given for the 3-D to 2-D transformation. Optimization of the transformation is shown to be NP-complete. Thus, simulated annealing is used to optimize the transformation.

[1] S. D. S. Malhi, H. E. Davis, R. J. Stierman, K. E. Bean, C. C. Driscoll, and P. K. Chatterjee,“Orthogonal chip mount—A 3D hybrid wafer scale integration technology,”Technical Digest, Int. Electron Devices Meeting, 1987, pp. 104–106.
[2] Y. Akasaka, T. Nishimura, and H. Nakata,“Trends in three-dimensional integration,”Solid State Technology, vol. 28, February, 1988.
[3] M. J. Little, R. D. Etchells, J. Grinberg, S. P. Laub, J. G. Nash, and M. W. Yung,“The 3-D computer,”inProc. Int. Conf. Wafer Scale Integration, 1989, pp. 55–64.
[4] Y. Inoue, K. Sugahara, S. Kusunoki, M. Nakaya, T. Nishimura, Y. Horiba, Y. Akasaka, and H. Nakata,“A three-dimensional static RAM,”IEEE Electron Device Lett., vol. 7, no. 5, pp. 327–329, 1986.
[5] T. Nishimura, Y. Inoue, K. Sugahara, S. Kusunoki, T. Kumanoto, S. Nakagawa, M.	Nakaya, Y. Horiba, and Y. Akasada,“Three dimensional IC for high performance image signal processor,”Technical Digest, Int. Electron Devices Meeting, 1987, pp. 111–114.
[6] T. Kunio, K. Oyama, Y. Hayashi, and M. Morimoto,“Three dimensional ICs, having four stacked active device layers,”Tech. Dig. Int. Electron Devices Meeting, 1989, pp. 837–840.
[7] H. M. Hazama, Takahashi, S. Kambayashi, M. Kemmochi, K. Tsuchiya, Y. Iida, K. Yano, T. Inoue, M. Yoshimi, T. Yoshii, and H. Tango,“Application of E-beam recrystallization	to three-layer image processor fabrication,”IEEE Trans. Electron Devices, vol. 38, no. 1, pp. 47–54, 1991.
[8] Y. Akasaka, S. Kusunoki, K. Sugahara, T. Nishimura, and H. Nakata,“Integrated MOS	devices in double active layers,”Symp. on VLSI Tech., pp. 90–91, 1983.
[9] S. Akiyama, M. Yoneda, S. Ogawa, N. Yoshii, and Y. Terui,“Fabrication technologies for multilayer CMOS device,”Symp. on VLSI Tech., 1984, pp. 28–29.
[10] K. Yamazaki, Y. Itoh, A. Wada, K. Morimoto, and Y. Tomita,“4-layer 3-D IC technologies for parallel signal processing,”Digest IEDM, pp. 599–602, 1990.
[11] N. Weste and K. Eshraghian, Principles of CMOS VLSI Design, Addison-Wesley, 1994.
[12] D. Braun, J. Burns, S. Devadas, H. K. Ma, K. Mayaram, F. Romeo, and A. Sangiovanni-Vincentelli,“Chameleon: A new multi-layer channel router,”inProc. 23rd Design Automation Conf., 1986, pp. 495–502.
[13] J. Cong, D. F. Wong, and C. L. Liu,“A new approach to three-or four-layer channel routing,”IEEE Trans. Computer-Aided Design, vol. 7, no. 10, pp. 1094–1103, 1988.
[14] R. J. Enbody and H. C. Du,“Near-optimal$n$-layer channel routing,”inProc. 23rd Design Automation Conf., pp. 708–714, 1986.
[15] R. I. Greenbey, A. T. Ishii, and A. L. Sangiovanni-Vincentelli,“MulCh: A multi-layer channel router using one, two, and three layer partitions,”inProc. ICCAD, pp. 88–91, 1988.
[16] T. Ohtsuki,Advances in CAD for VLSI: Vol. 4, Layout Design and Verification.New York: Elsevier Science Pub. Co., 1986.
[17] C. Y. Lee,“An algorithm for path connections and its applications,”IRE Trans. Electronic Computers, vol. 10, Sept., pp. 346–354, 1961.
[18] S. B. Akers, Jr.,“A modification of Lee's path connection algorithm,”IEEE Trans. Electronic Comput., vol. 16, no. 2, pp. 97–98, 1967.
[19] J. H. Hoel,“Some variations of Lee's algorithm,”IEEE Trans. Comput., vol. 25, no. 1, pp. 19–24, 1976.
[20] W. A. Dees, Jr. and R. J. Smith, II,“Performance of interconnection rip-up and reroute strategies,”inProc. 18th Design Automation Conf., 1981, pp. 382–390.
[21] W. A. Dees, Jr. and P. G. Karger,“Automated rip-up and reroute techniques,”inProc. 19th Design Automation Conf., 1982, pp. 432–439.
[22] A. Hashimoto and J. Stevens,“Wire routing by optimizing channel assignment within large apertures,”inProc. 8th Design Automation Workshop, 1971, pp. 155–169.
[23] J. Reed, A. Sangiovanni-Vincentelli, and M. Santomauro,“A new symbolic channel router: YACR2,”IEEE Trans. Computer-Aided Design, vol. 4, no. 7, pp. 208–219, 1985.
[24] M. Burstein and K. Pelavin,“Hierarchical wire routing,”IEEE Trans. Computer-Aided Design, vol. 2, no. 10, pp. 223–234, 1983.
[25] H. Shin and A. Sangiovanni-Vincentelli,“A detailed router based on incremental routing modifications: mighty,”IEEE Trans. Computer-Aided Design, vol. 6, no. 11, pp. 942–955, 1987.
[26] D. N. Deutsch,“A“dogleg”channel router,”inProc. 13th Design Automat. Conf., pp. 425–433, 1976.
[27] R. Joobbani and D. P. Siewiorek,“WEAVER: A knowledge-based routing expert,”IEEE Design and Test of Computers (Magazine), vol. 3, pp. 12–23, Feb. 1986.
[28] R. L. Rivest and C. M. Fiduccia,“A“greedy”channel router,”inProc. 19th Design	Automation Conf., 1982, pp. 418–424.
[29] T. Yoshimura and E. S. Kuh,“Efficient algorithms for channel routing,”IEEE Trans. Computer-Aided Design, vol. 1, no. 1, pp. 25–35, 1982.
[30] S. Kimura, N. Kubo, T. Chiba, and I. Nishioka,“An automatic routing scheme for general cell LSI,”IEEE. Trans. CAD, vol. 2, no. 10, pp. 285–292, 1983.
[31] H. Cai and R. H. J. M. Otten,“Conflict-free channel definition in building-block layout,”	IEEE Trans. CAD, vol. 8, no. 9, pp. 981–988, 1989.
[32] Y. L. Lin, Y. C. Hsu, and F. S. Tsai,“Hybrid routing,”IEEE. Trans. CAD, vol. 9, no. 2, pp. 151–157, 1990.
[33] C. C. Tong,“Routing in three-dimensional microelectronic structures,”Ph.D. dissertation, University of Texas at Austin, 1991.
[34] J. Cong and C. L. Liu,“Over-the-cell channel routing,”IEEE Trans. Computer-Aided Design, vol. 9, no. 4, pp. 408–418, 1990.
[35] S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi,“Optimization by simulated annealing,”Science,vol. 220, no. 5, pp. 671–680, 1983.

Index Terms:
Silicon-on-insulator, three-dimensional chip, three-dimensional routing, channel routing, inter-layer routing, intra layer routing, NP-routing, constraint graph, computed-aided design.
Citation:
Chao Chi Tong, Chuan-lin Wu, "Routing in a Three-Dimensional Chip," IEEE Transactions on Computers, vol. 44, no. 1, pp. 106-117, Jan. 1995, doi:10.1109/12.368006
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