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P. Ienne, M.A. Viredaz, "BitSerial Multipliers and Squarers," IEEE Transactions on Computers, vol. 43, no. 12, pp. 14451450, December, 1994.  
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@article{ 10.1109/12.338107, author = {P. Ienne and M.A. Viredaz}, title = {BitSerial Multipliers and Squarers}, journal ={IEEE Transactions on Computers}, volume = {43}, number = {12}, issn = {00189340}, year = {1994}, pages = {14451450}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.338107}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  BitSerial Multipliers and Squarers IS  12 SN  00189340 SP1445 EP1450 EPD  14451450 A1  P. Ienne, A1  M.A. Viredaz, PY  1994 KW  adders; computational complexity; digital arithmetic; multiplying circuits; bitserial multipliers; squarers; clock cycles; datalatency; combinational delay; adders; latency cycles; two's complement numbers; VLSI libraries. VL  43 JA  IEEE Transactions on Computers ER   
Traditional bitserial multipliers present one or more clock cycles of datalatency. In some situations, it is desirable to obtain the output after only a combinational delay, as in serial adders and subtracters. A serial multiplier and a squarer with no latency cycles are presented here. Both accept unsigned or signextended two's complement numbers and produce an arbitrarily long output. They are fully modular and thus good candidates for introduction in VLSI libraries.
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