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Bit-Serial Multipliers and Squarers
December 1994 (vol. 43 no. 12)
pp. 1445-1450

Traditional bit-serial multipliers present one or more clock cycles of data-latency. In some situations, it is desirable to obtain the output after only a combinational delay, as in serial adders and subtracters. A serial multiplier and a squarer with no latency cycles are presented here. Both accept unsigned or sign-extended two's complement numbers and produce an arbitrarily long output. They are fully modular and thus good candidates for introduction in VLSI libraries.

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Index Terms:
adders; computational complexity; digital arithmetic; multiplying circuits; bit-serial multipliers; squarers; clock cycles; data-latency; combinational delay; adders; latency cycles; two's complement numbers; VLSI libraries.
Citation:
P. Ienne, M.A. Viredaz, "Bit-Serial Multipliers and Squarers," IEEE Transactions on Computers, vol. 43, no. 12, pp. 1445-1450, Dec. 1994, doi:10.1109/12.338107
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