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J. Lopez, E.L. Zapata, "Unified Architecture for Divide and Conquer Based Tridiagonal System Solvers," IEEE Transactions on Computers, vol. 43, no. 12, pp. 14131425, December, 1994.  
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@article{ 10.1109/12.338101, author = {J. Lopez and E.L. Zapata}, title = {Unified Architecture for Divide and Conquer Based Tridiagonal System Solvers}, journal ={IEEE Transactions on Computers}, volume = {43}, number = {12}, issn = {00189340}, year = {1994}, pages = {14131425}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.338101}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Unified Architecture for Divide and Conquer Based Tridiagonal System Solvers IS  12 SN  00189340 SP1413 EP1425 EPD  14131425 A1  J. Lopez, A1  E.L. Zapata, PY  1994 KW  parallel architectures; divide and conquer methods; unified architecture; divide and conquer based tridiagonal system solvers; unified parallel architecture; Successive Doubling; Recursive Doubling; Parallel Cyclic Reduction methods; systolic data flow; wired control section; constant geometry cyclic reduction architecture; VLSI. VL  43 JA  IEEE Transactions on Computers ER   
The solution of tridiagonal systems is a topic of great interest in many areas of numerical analysis. Several algorithms have recently been proposed for solving triadiagonal systems based on the Divide and Conquer (DC) strategy. In this work we propose a unified parallel architecture for DC algorithms which present the data flows of the Successive Doubling, Recursive Doubling and Parallel Cyclic Reduction methods. The architecture is based in the perfect unshuffle permutation, which transforms these data flows into a constant geometry one. The partition of the data arises in a natural manner, giving way to a systolic data flow with a wired control section. We conclude that the constant geometry Cyclic Reduction architecture is the most appropriate one for solving tridiagonal systems and, from the point of view of integration in VLSI technology, is the one which uses the least amount of area and the smallest number of pins.
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