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The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis
December 1994 (vol. 43 no. 12)
pp. 1398-1406

This paper summarizes a practical experiment in designing a defect tolerant microprocessor and presents the underlying principles. Unlike memory integrated circuits, microprocessors have an irregular structure which complicates both the task of incorporating redundancy for defect tolerance in the design and the task of analyzing the resulting yield increase. The main goal of this paper is to present the detailed yield analysis of a defect tolerant microprocessor with an irregular structure which has been successfully fabricated. The approaches employed for achieving the goal of yield enhancement in the data path and the control part of the microprocessor are described first. Then, the yield enhancement due to the incorporated redundancy is analyzed. Finally, some practical and theoretical conclusions are drawn.

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Index Terms:
redundancy; circuit optimisation; integrated circuit yield; fault tolerant computing; microprocessor chips; Hyeti defect tolerant microprocessor; cost-effectiveness analysis; redundancy; yield enhancement.
Citation:
R. Leveugle, Z. Koren, I. Koren, G. Saucier, N. Wehn, "The Hyeti Defect Tolerant Microprocessor: A Practical Experiment and its Cost-Effectiveness Analysis," IEEE Transactions on Computers, vol. 43, no. 12, pp. 1398-1406, Dec. 1994, doi:10.1109/12.338099
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