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R. Cypher, L. Gravano, "StorageEfficient, DeadlockFree Packet Routing Algorithms for Torus Networks," IEEE Transactions on Computers, vol. 43, no. 12, pp. 13761385, December, 1994.  
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@article{ 10.1109/12.338097, author = {R. Cypher and L. Gravano}, title = {StorageEfficient, DeadlockFree Packet Routing Algorithms for Torus Networks}, journal ={IEEE Transactions on Computers}, volume = {43}, number = {12}, issn = {00189340}, year = {1994}, pages = {13761385}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.338097}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
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TY  JOUR JO  IEEE Transactions on Computers TI  StorageEfficient, DeadlockFree Packet Routing Algorithms for Torus Networks IS  12 SN  00189340 SP1376 EP1385 EPD  13761385 A1  R. Cypher, A1  L. Gravano, PY  1994 KW  multiprocessor interconnection networks; VLSI; packet switching; deadlockfree packet routing algorithms; torus networks; torus interconnection networks; minimal length packet routing; VLSI implementation. VL  43 JA  IEEE Transactions on Computers ER   
We present two new packet routing algorithms for parallel computers with torus interconnection networks of arbitrary size and dimension. Both algorithms use only minimal length paths, are fully adaptive in the sense that all minimal length paths may be used to avoid congestion, and are free of deadlock, livelock and starvation. Algorithm 1 requires only three central queues per routing node. It is the first known minimal length packet routing algorithm for torus networks which requires a constant number of queues per node, regardless of the size and dimension of the torus. In fact, the requirement of three queues per node is optimal, as no such algorithm is possible when all nodes have two or fewer queues. Algorithm 2 requires only that each node have two input buffers per edge. It is the first known minimalfullyadaptive packet routing algorithm for torus networks which does not require central queues and which does not require any node to have more than two input or two output buffers per edge. Both algorithms are simple and appear to be wellsuited to VLSI implementation. They can be used with either storeandforward or virtual cutthrough routing.
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