This Article 
 Bibliographic References 
 Add to: 
Storage-Efficient, Deadlock-Free Packet Routing Algorithms for Torus Networks
December 1994 (vol. 43 no. 12)
pp. 1376-1385

We present two new packet routing algorithms for parallel computers with torus interconnection networks of arbitrary size and dimension. Both algorithms use only minimal length paths, are fully adaptive in the sense that all minimal length paths may be used to avoid congestion, and are free of deadlock, livelock and starvation. Algorithm 1 requires only three central queues per routing node. It is the first known minimal length packet routing algorithm for torus networks which requires a constant number of queues per node, regardless of the size and dimension of the torus. In fact, the requirement of three queues per node is optimal, as no such algorithm is possible when all nodes have two or fewer queues. Algorithm 2 requires only that each node have two input buffers per edge. It is the first known minimal-fully-adaptive packet routing algorithm for torus networks which does not require central queues and which does not require any node to have more than two input or two output buffers per edge. Both algorithms are simple and appear to be well-suited to VLSI implementation. They can be used with either store-and-forward or virtual cut-through routing.

[1] K. E. Batcher, "Design of a massively parallel processor."IEEE Trans. Comput., vol. 29, no. 9, pp. 836-846, Sept. 1980.
[2] P. Berman, L. Gravano, G.D. Pifarré, and J. L. C. Sanz, "Adaptive deadlock- and livelock-free routing with all minimal paths in torus networks," inProc. 4th Symp. Parallel Algorithms and Architectures (SPAA), 1992.
[3] G.-M. Chiu, S. Chalasani, and C. S. Raghavendra, "Flexible, fault-tolerant routing criteria for circuit-switched hypercubes," in11th Int. Conf. Distrib. Computing Syst., 1991.
[4] B. Cypher and D. Gavano, "Requirements for deadlock-free, adaptive packet routing, " inProc. 11th ACM Symp. Principles of Distrib. Computing, 1992, pp. 25-33.
[5] W. J. Dally, "Fine-grain message passing concurrent computers," inProc. Third Conf. Hypercube Concurrent Comput., vol. 1, Pasadena, CA, pp. 2-12, Jan. 1988.
[6] W. J. Dally and H. Aoki, "Deadlock-free adaptive routing in multicomputer networks using virtual channels,"IEEE Trans. Parallel Distrib. Syst., vol. 4, pp. 466-475, Apr. 1993.
[7] W.J. Dally and C.L. Seitz, "Deadlock-Free Message Routing in Multiprocessor Interconnection Networks,"IEEE Trans. Computers, Vol. C-36, No. 5, May 1987, pp. 547-553.
[8] J. Duato, "Deadlock-free adaptive routing algorithms for multicomputers: Evaluation of a new algorithm," inProc. 3rd IEEE Int. Symp. Parallel Distributed Processing, Dec. 1991.
[9] S. A. Felperin, H. Laftitte, G. Buranits, and J. L. C. Sanz, "Deadlock-free minimal packet routing in the torus network," Tech. Rep. TR 91-22, IBM Argentina. CRAAG, 1991.
[10] B. Gavish, P. M. Merlin, and P. J. Schweitzer, "Minimal buffer requirements for avoiding store-and-forward deadlock," Tech. Rep. RC 6672. IBM T. J. Watson Res. Center, Aug. 1977.
[11] C. J. Glass and L. M. Ni, "The turn model for adaptive routing," inProc. 19th Annu. Int. Symp. Comput. Architecture, May 1992, pp. 278-287.
[12] I. S. Gopal, "Prevention of store-and-forward deadlock in computer networks,"IEEE Trans. Commun., vol. COM-33, no. 12, pp. 1258-1264, Dec. 1985.
[13] L. Gravano, G. D. Pifarré, G. Denicolay, and J. L. C. Sanz, "Adaptive deadlock-free wormhole routing in hypercubes," inProc. 6th Int. Parallel Processing Symp., 1992.
[14] K. D. Gunther, "Prevention of deadlocks in packet-switched data transport systems,"IEEE Trans. Commun., vol. COM-29, no. 4, pp. 512-524, Apr. 1981.
[15] P. A. J. Hilbers and J. J. Lukkien, "Deadlock-free message routing in multicomputer networks,"Distrib. Computing, vol. 3, pp. 178-186, 1989.
[16] C. R. Jesshope, P. R. Miller, and J. T. Yantchev, "High performance communication in processor networks," inProc. 16th Annu. Int. Symp. Comput. Architecture, pp. 150-157, May 1989.
[17] P. Kermani and L. Kleinrock, "Virtual cut-through: A new computer communications switching technique," Comput. New., vol. 3, pp. 267-296, 1979.
[18] S. Konstantinidou, "Adaptive, minimal routing in hypercubes," in6th MIT Conf. Advanced Res. VLSI, 1990, pp. 139-153.
[19] S. Konstantinidou and L. Snyder, "The Chaos router: A practical application of randomization in network routing," in2nd Ann. ACM SPAA, 1990, pp. 21-30.
[20] T. Leighton, F. Makedon, and I. G. Tollis, "A 2n-2 step algorithm for routing in ann×narray with constant size queues," inProc. ACM Symp. Parallel Algorithms and Architectures, 1989, pp. 328-335.
[21] D. H. Linder and J. C. Harden, "An adaptive and fault tolerant wormhole routing strategy fork-aryn-cubes,"IEEE Trans. Comput., vol. 40, no. 1, pp. 2-12, Jan. 1991.
[22] P. M. Merlin and P. J. Schweitzer, "Deadlock avoidance in store-and-forward networks--I: Store-and-forward deadlock,"IEEE Trans. Commun., vol. COM-28, pp. 345-354, Mar. 1980.
[23] MP-1 family data-parallel computers, 1987. MasPar Computer Corporation, 749 North Mary Ave., Sunnyvale, CA.
[24] M. O. Noakes and W. J. Dally, "System design of the J-Machine," inProc. Sixth MIT Conf. Advanced Res. VLSI, MIT Press, 1990, pp. 179-194.
[25] G. D. Pifarré, L. Gravano, S. A. Felperin, and J. L.C. Sanz, "Fully adaptive minimal deadlock-free packet routing in hypercubes, meshes, and other networks," inProc. 3rd Ann. ACM Symp Parallel Algorithms and Architectures, 1991.
[26] C. L. Seitzet al., "The architecture and programming of the Ametek Series 2010 Multicomputer," inProc. Third Conf. Hypercube Concurrent Comput. Appl., ACM, Jan. 1988, pp. 33-37.
[27] C. D. Thompson, "Area-time complexity for VLSI," inProc. Eleventh Annu. ACM Symp. Theory Comput., 1979, pp. 81-88.
[28] S. Toueg and J. D. Ullman, "Deadlock-free packet switching networks,"SIAM J. Computing, vol. 10, no. 3, pp. 594-611, Aug. 1981.
[29] J. Yantchev and C. R. Jesshope, "Adaptive, low latency, deadlock-free packet routing for networks of processors,"IEEE Proc. Pt. E, vol. 136, no. 3, pp. 178-186, May 1989.

Index Terms:
multiprocessor interconnection networks; VLSI; packet switching; deadlock-free packet routing algorithms; torus networks; torus interconnection networks; minimal length packet routing; VLSI implementation.
R. Cypher, L. Gravano, "Storage-Efficient, Deadlock-Free Packet Routing Algorithms for Torus Networks," IEEE Transactions on Computers, vol. 43, no. 12, pp. 1376-1385, Dec. 1994, doi:10.1109/12.338097
Usage of this product signifies your acceptance of the Terms of Use.