This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
A Functional Approach to Efficient Fault Detection in Iterative Logic Arrays
December 1994 (vol. 43 no. 12)
pp. 1365-1375

We consider the problem of fault detection in iterative logic arrays (ILA's). This problem has been studied by numerous researchers for many years. The results can be succinctly summarized by stating that one dimensional arrays can be effectively analyzed and significant results obtained while the problems associated with arrays of dimension two or greater appear to be intractable (i.e., NP-complete) for general arbitrary ILA's. However as is the case for many other switching theory problems, general case problems that are intractable, can be readily handled for the special cases defined by functions commonly encountered in practice. We show that arrays of dimension two or greater can be effectively tested for the case when the functions defined by the arrays have inverses. Many specific arithmetic functions satisfy this property. We also show that even for functions which do not satisfy this property, the functional approach simplifies testing problems considerably.

[1] M. Abramovici, M. A. Breuer and A. D. Friedman,Digital Systems Testing and Testable Design. New York: Computer Science Press, 1990.
[2] S. Ameen, "Easily testable design of massively parallel computing systems," Ph.D. thesis (in progress).
[3] W.-T. Cheng and J. H. Patel, "Testing in two-dimensional iterative logic arrays," inDig. 16th Int. Symp. Fault-Tolerant Comput., July 1986.
[4] F. J. O. Dias, "Truth-table verification of an iterative logic array,"IEEE Trans. Comput., vol. C-25, pp. 605-613, June 1976.
[5] A. D. Friedman and P. R. Menon,Fault Detection in Digital Circuits. Englewood Cliffs, NJ: Prentice Hall, 1971.
[6] A. D. Friedman, "Easily testable iterative systems,"IEEE Trans. Comput., vol. C-22, pp. 1061-1064, Dec. 1973.
[7] W. H. Kautz, "Testing for faults in combinational cellular logic arrays," inProc. 8th Anna. Symp. Switching and Automata Theory, 1967, pp. 161-174.
[8] P. R. Menon and A. D. Friedman, "Fault detection in iterative logic arrays,"IEEE Trans. Comput., vol. C-20, pp. 524-435, May 1971.
[9] J. P. Shen and F. J. Ferguson, "The design of easily testable VLSI array multipliers,"IEEE Trans. Comput., vol. C-33, pp. 554-560, June 1984.
[10] T. Sridhar and J. P. Hayes, "A functional approach to testing bit-sliced microprocessors,"IEEE Trans. Comput., vol. C-30, pp. 563-571, Aug. 1981.
[11] T. Sridhar and J. P. Hayes, "Design of Easily Testable Bit-Sliced Systems,"IEEE Trans. Comput., Vol. C-30, pp. 842-854, November 1981.

Index Terms:
logic arrays; fault diagnosis; logic testing; fault location; functional approach; fault detection; iterative logic arrays; one dimensional arrays; NP-complete; arithmetic functions.
Citation:
A.D. Friedman, "A Functional Approach to Efficient Fault Detection in Iterative Logic Arrays," IEEE Transactions on Computers, vol. 43, no. 12, pp. 1365-1375, Dec. 1994, doi:10.1109/12.338096
Usage of this product signifies your acceptance of the Terms of Use.