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N.S.V. Rao, S. Toida, "On PolynomialTime Testable Combinational Circuits," IEEE Transactions on Computers, vol. 43, no. 11, pp. 12981308, November, 1994.  
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@article{ 10.1109/12.324562, author = {N.S.V. Rao and S. Toida}, title = {On PolynomialTime Testable Combinational Circuits}, journal ={IEEE Transactions on Computers}, volume = {43}, number = {11}, issn = {00189340}, year = {1994}, pages = {12981308}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.324562}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  On PolynomialTime Testable Combinational Circuits IS  11 SN  00189340 SP1298 EP1308 EPD  12981308 A1  N.S.V. Rao, A1  S. Toida, PY  1994 KW  combinatorial circuits; logic testing; computational complexity; fault location; polynomialtime testable combinational circuits; circuit decompositions; fanoutreconvergent pairs; PTT classes; NPcompleteness; Boolean formulae; affine classes; stuckat faults; combinational circuits. VL  43 JA  IEEE Transactions on Computers ER   
The problems of identifying several nontrivial classes of PolynomialTime Testable (PTT) circuits are shown to be NPcomplete or harder. First, PTT classes obtained by using circuit decompositions proposed by Fujiwara (1988) and Chakradhar et al. (1990) are considered. Another type of decompositions, based on fanoutreconvergent (fr) pairs, which also lead to PTT classes are proposed. The problems of obtaining these decompositions, and also some structurally similar general graph decompositions, are shown to be NPcomplete or harder. Then, the problems of recognizing PTT classes formed by the Boolean formulae belonging to the weakly positive, weakly negative, bijunctive and affine classes are shown to be NPcomplete.
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