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Issue No.11 - November (1994 vol.43)
pp: 1298-1308
ABSTRACT
<p>The problems of identifying several nontrivial classes of Polynomial-Time Testable (PTT) circuits are shown to be NP-complete or harder. First, PTT classes obtained by using circuit decompositions proposed by Fujiwara (1988) and Chakradhar et al. (1990) are considered. Another type of decompositions, based on fanout-reconvergent (f-r) pairs, which also lead to PTT classes are proposed. The problems of obtaining these decompositions, and also some structurally similar general graph decompositions, are shown to be NP-complete or harder. Then, the problems of recognizing PTT classes formed by the Boolean formulae belonging to the weakly positive, weakly negative, bijunctive and affine classes are shown to be NP-complete.</p>
INDEX TERMS
combinatorial circuits; logic testing; computational complexity; fault location; polynomial-time testable combinational circuits; circuit decompositions; fanout-reconvergent pairs; PTT classes; NP-completeness; Boolean formulae; affine classes; stuck-at faults; combinational circuits.
CITATION
N.S.V. Rao, S. Toida, "On Polynomial-Time Testable Combinational Circuits", IEEE Transactions on Computers, vol.43, no. 11, pp. 1298-1308, November 1994, doi:10.1109/12.324562
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