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| R.F. Tinder, R.I. Klaus, J.A. Snodderley, "High-Speed Microprogrammable Asynchronous Controller Modules," IEEE Transactions on Computers, vol. 43, no. 10, pp. 1226-1232, October, 1994. | |||
| BibTex | x | ||
| @article{ 10.1109/12.324548, author = {R.F. Tinder and R.I. Klaus and J.A. Snodderley}, title = {High-Speed Microprogrammable Asynchronous Controller Modules}, journal ={IEEE Transactions on Computers}, volume = {43}, number = {10}, issn = {0018-9340}, year = {1994}, pages = {1226-1232}, doi = {http://doi.ieeecomputersociety.org/10.1109/12.324548}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - High-Speed Microprogrammable Asynchronous Controller Modules IS - 10 SN - 0018-9340 SP1226 EP1232 EPD - 1226-1232 A1 - R.F. Tinder, A1 - R.I. Klaus, A1 - J.A. Snodderley, PY - 1994 KW - logic arrays; finite state machines; finite automata; logic design; sequential circuits; microprogrammable asynchronous controller modules; high-speed; programmable logic devices; asynchronous controllers; asynchronous modules; asynchronous sequencers; asynchronous state machines; high-speed controllers; modules; programmable controllers; sequencers. VL - 43 JA - IEEE Transactions on Computers ER - | |||
A unique family of high-speed, microprogrammable asynchronous controller (MAC) modules is described in this correspondence. Each MAC module consists of two fundamental mode machines that communicate by means of a handshake interface that permits it to be driven by any programmable logic device including ROM's. Any state machine controller designed with a MAC module will operate free of critical races, essential hazards and output race glitches, and will have static hazard-free state variables. A multiplicity of programmable logic devices can be used to drive one or more MAC modules to achieve complex, but reliable, asynchronous, time-shared and/or parallel processing of data. Individual MAC modules having state variables numbering l,m,n,...can be cascaded to produce an available system state capacity of 2/sup lspl times/2/sup mspl times/2/sup nspl times/...states with up to (l+m+n+...)-way transition capability, all without compromising speed or reliability.
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