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High-Speed Microprogrammable Asynchronous Controller Modules
October 1994 (vol. 43 no. 10)
pp. 1226-1232

A unique family of high-speed, microprogrammable asynchronous controller (MAC) modules is described in this correspondence. Each MAC module consists of two fundamental mode machines that communicate by means of a handshake interface that permits it to be driven by any programmable logic device including ROM's. Any state machine controller designed with a MAC module will operate free of critical races, essential hazards and output race glitches, and will have static hazard-free state variables. A multiplicity of programmable logic devices can be used to drive one or more MAC modules to achieve complex, but reliable, asynchronous, time-shared and/or parallel processing of data. Individual MAC modules having state variables numbering l,m,n,...can be cascaded to produce an available system state capacity of 2/sup lspl times/2/sup mspl times/2/sup nspl times/...states with up to (l+m+n+...)-way transition capability, all without compromising speed or reliability.

[1] L. L. Mate, S. Das, and H. Y. H. Chuang, "A logic hazard detection and elimination method,"Inform. Contr., vol. 26. pp. 351-368, 1974.
[2] L. Lavagno, K. Keutzer, and A. Sangiovanni-Vincentelli, "Algorithms for synthesis of hazard-free asynchronous circuits,"ACM/IEEE Design Automation Conf. Proc., 1991, pp. 302-308.
[3] S. H. Unger,Asynchronous Sequential Switching Theory. New York: Wiley, 1969.
[4] R. F. Tinder,Digital Engineering Design: A Modern Approach. Englewood Cliffs, NJ: Prentice-Hall, 1991.
[5] D. L. Dietmeyer,Logic Design of Digital Systems. Boston, MA: Allyn and Bacon, 1979.
[6] E. J. McCluskey,Logic Design Principles. Englewood Cliffs, NJ: Prentice-Hall, 1986.
[7] L. A. Glasser and D. W Dobberpuhl,The Design and Analysis of VLSI Circuits. Reading, MA: Addison-Wesley, 1985.
[8] Signitics Fast Logic,Phillips Data Handbook, Phillips, pp. 6-755, 1989.
[9] A. Blake, A. Zisserrman, and G. Knowles, "Surface descriptions from stereo and shading,"Image Vision Comput., vol. 3, pp. 183-191, 1985 (also included in-[20]).
[10] L. S. Kim and R. W. Dutton, "Metastability of CMOS latch/flip-flop,"IEEE J. Solid State Circuits, vol. 25, no. 4, pp. 942-951, Aug. 1990.
[11] T. J. Chaney and C. E. Molnar, "Anomalous behavior of synchronizer and arbiter circuits,"IEEE Trans. Comput., vol. C-22, pp. 421-422, Apr. 1973.
[12] T. Sakurai, "Optimization of CMOS arbiter and synchronizer circuits with submicrometer MOSFET's,"IEEE J. Solid State Circuits, vol. 23, no. 4, pp. 901-906, Aug. 1988.
[13] T. J. Chancy, "A comprehensive bibliography on synchronizers and arbiters," Technical Memo. No. 306, Inst. for Biomedical Computing, Washington Univ., St. Louis, MO, 1985.

Index Terms:
logic arrays; finite state machines; finite automata; logic design; sequential circuits; microprogrammable asynchronous controller modules; high-speed; programmable logic devices; asynchronous controllers; asynchronous modules; asynchronous sequencers; asynchronous state machines; high-speed controllers; modules; programmable controllers; sequencers.
Citation:
R.F. Tinder, R.I. Klaus, J.A. Snodderley, "High-Speed Microprogrammable Asynchronous Controller Modules," IEEE Transactions on Computers, vol. 43, no. 10, pp. 1226-1232, Oct. 1994, doi:10.1109/12.324548
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