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Area Time Trade-Offs in Micro-Grain VLSI Array Architectures
October 1994 (vol. 43 no. 10)
pp. 1121-1128

We study the relative performance of three different massively parallel fine-grain, VLSI, control-flow architectures. The processor architectures being considered are: an associative memory architecture, a Mux-based SIMD architecture and a modification of the Mux-based architecture using RAMs making it suitable for systolic MIMD/MISD computation. All three architectures are organized as two-dimensional, near-neighbor mesh connected, array of processors. All three are very similar in their construction, and in their control and data-flow requirements. The custom hardware for all three architectures was built using the same technology. We compare and contrast the performance of these three VLSI architectures for a select set of applications. To evaluate the computational power of the three architectures we use the area time product, AT, as the metric. The three designs are known to perform well in their niche applications and we find that for non-niche applications all three designs are comparable in power to within a small constant factor. The performance of the Mux-based SIMD architecture is better in general than the other two in terms of speed though the associative architecture is found to out-perform the SIMD architecture for certain numeric applications like the FFT and matrix multiplication in the AT sense.

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Index Terms:
VLSI; parallel architectures; performance evaluation; area time trade-offs; micro-grain VLSI array architectures; performance; massively parallel control-flow architectures; associative memory architecture; Mux-based SIMD architecture; RAMs; systolic MIMD/MISD computation; data-flow requirements; FFT; matrix multiplication.
Citation:
R. Singh Bajwa, R.M. Owens, M.J. Irwin, "Area Time Trade-Offs in Micro-Grain VLSI Array Architectures," IEEE Transactions on Computers, vol. 43, no. 10, pp. 1121-1128, Oct. 1994, doi:10.1109/12.324538
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