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Multiple Fault Detection in Parity Checkers
September 1994 (vol. 43 no. 9)
pp. 1096-1099

Parity checkers are widely used in digital systems to detect errors when systems are in operation. Since parity checkers are monitoring circuits, their reliability must be guaranteed by performing a thorough testing. In this work, multiple fault detection of parity checkers is investigated. We have found that all multiple stuck-at faults occurring on a parity tree can be completely detected using test patterns provided by the identity matrix plus zero vector. The identity matrix contains 1's on the main diagonal and 0's elsewhere; while the zero vector contains 0's. The identity matrix vectors can also detect all multiple general bridging faults, if the bridgings result in a wired-AND effect. However, test patterns generated from the identity matrix and binary matrix are required to detect a majority of the multiple bridging faults which yield wired-OR connections. Note that the binary matrix contains two 1's at each column of the matrix.

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Index Terms:
fault location; logic testing; multiple fault detection; parity checkers; digital systems; monitoring circuits; reliability; multiple stuck-at faults; identity matrix; zero vector; wired-OR connections; binary matrix.
Citation:
Wen-Ben Jone, Cheng-Juei Wu, "Multiple Fault Detection in Parity Checkers," IEEE Transactions on Computers, vol. 43, no. 9, pp. 1096-1099, Sept. 1994, doi:10.1109/12.312118
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